The ’HC597 and CD74HCT597 are high-speed silicon gate CMOS devices that are pin compatible with the LSTTL 597 devices. Each device consists of an 8-flip-flop input register and an 8-bit parallel-in/serial-in, serial-out shift register. Each register is controlled by its own clock. A "low" on the parallel load input (PL\) shifts parallel stored data asynchronously into the shift register. A "low" master input (MR\) clears the shift register. Serial input data can also be synchronously shifted through the shift register when PL\ is high.
CD54HC597 | |
Voltage Nodes(V) | 5, 3.3 |
Technology Family | HC |
Rating | Military |
器件 | 状态 | 温度 | 价格 | 封装 | 引脚 | 封装数量 | 封装载体 | 丝印标记 |
CD54HC597F | ACTIVE | -55 to 125 | 5.09 | 1ku | CDIP (JT) | 16 | 1 | TUBE | |
CD54HC597F3A | ACTIVE | -55 to 125 | 5.91 | 1ku | CDIP (JT) | 16 | 1 | TUBE |
器件 | 环保计划* | 铅/焊球涂层 | MSL 等级/回流焊峰 | 环保信息与无铅 (Pb-free) | DPPM / MTBF / FIT 率 |
CD54HC597F | TBD | A42 | N/A for Pkg Type | CD54HC597F | CD54HC597F |
CD54HC597F3A | TBD | A42 | N/A for Pkg Type | CD54HC597F3A | CD54HC597F3A |