SN54107 具有清零功能的双路 J-K 触发器
The '107 contain two independent J-K flip-flops with individual J-K, clock, and direct clear inputs. The '107 is a positive pulse-triggered flip-flop. The J-K input data is loaded into the master while the clock is high and transferred to the slave and the outputs on the high-to-low clock transition. For these devices the J and K inputs must be stable while the clock is high.
The 'LS107A contain two independent negative-edge-triggered flip-flops. The J and K inputs must be stable prior to the high-to-low clock transition for predictable operation. When the clear is low, it overrides the clock and data inputs forcing the Q output low and the Q\ output high.
The SN54107 and the SN54LS107A are characterized for operation over the full military temperature range of -55°C to 125°C.
| SN54107 | |
| Voltage Nodes(V) | 5 |
| Vcc range(V) | 4.5 to 5.5 |
| Input Level | TTL |
| Output Level | TTL |
| Output | 2S |
| No. of Bits | 2 |
| Technology Family | TTL |
| Rating | Military |
SN54107 特性
- Package Options Include Plastic “Small Outline" Packages, Ceramic Chip Carriers, and Plastic and Ceramic DIPs
- Dependable Texas Instruments Quality and Reliability
SN54107 芯片订购指南
| 器件 | 状态 | 温度 | 价格 | 封装 | 引脚 | 封装数量 | 封装载体 | 丝印标记 |
| JM38510/00203BCA | ACTIVE | -55 to 125 | 6.16 | 1ku | CDIP (J) | 14 | 1 | TUBE | JM38510/ 00203BCA |
| SN54107J | ACTIVE | -55 to 125 | 3.68 | 1ku | CDIP (J) | 14 | 1 | TUBE | SN54107J |
| SNJ54107J | ACTIVE | -55 to 125 | 4.34 | 1ku | CDIP (J) | 14 | 1 | TUBE | SNJ54107J |
SN54107 质量与无铅数据
| 器件 | 环保计划* | 铅/焊球涂层 | MSL 等级/回流焊峰 | 环保信息与无铅 (Pb-free) | DPPM / MTBF / FIT 率 |
| JM38510/00203BCA | TBD | A42 | N/A for Pkg Type | JM38510/00203BCA | JM38510/00203BCA |
| SN54107J | TBD | A42 | N/A for Pkg Type | SN54107J | SN54107J |
| SNJ54107J | TBD | A42 | N/A for Pkg Type | SNJ54107J | SNJ54107J |
SN54107 应用技术支持与电子电路设计开发资源下载
- SN54107 数据资料 dataSheet 下载.PDF
- TI 德州仪器触发器/锁存器/寄存器产品选型与价格 . xls
- Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
- Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
- TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
- Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
- CMOS Power Consumption and CPD Calculation (PDF 89 KB)
- Designing With Logic (PDF 186 KB)
- Live Insertion (PDF 150 KB)
- Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
- Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- LOGIC Pocket Data Book (PDF 6001 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- Logic Cross-Reference (PDF 2938 KB)
