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SN54173 具有三态输出的 4 位 D 类寄存器

The '173 and 'LS173A 4-bit registers include D-type flip-flops featuring totem-pole 3-state outputs capable of driving highly capacitive
or relatively low-impedance loads. The high-impedance third state and increased high-logic-level drive provide these flip-flops with the capability of being connected directly to and driving the bus lines in a bus-organized system without need for interface or pull-up components. Up to 128 of the SN74173 or SN74LS173A outputs can be connected to a common bus and still drive two Series 54/74 or 54LS/74LS TTL normalized loads, respectively. Similarly, up to 49 of the SN54173 or SN54LS173A outputs can be connected to a common bus and drive one additional Series 54/74 or 54LS/74LS TTL normalized load, respectively

	SN54173
Voltage Nodes(V)	5
Technology Family	TTL
Rating	Military

SN54173 特性

• 3-State Outputs Interface Directly With System Bus
• Gated Output-Control LInes for Enabling or Disabling the Outputs
• Fully Independent Clock Virtually Eliminates Restrictions for Operating in One of Two Modes:
  • Parallel Load
  • Do Nothing (Hold)
• For Application as Bus Buffer Registers
• Package Options Include Plastic Small-Outline (D) Packages, Ceramic Flat (W) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) DIPs

SN54173 芯片订购指南

器件	状态	温度	价格（美元）	封装 | 引脚	封装数量 | 封装载体	丝印标记
SN54173J	ACTIVE	-55 to 125	4.13 | 1ku	CDIP (J) | 16	1 | TUBE
SNJ54173J	ACTIVE	-55 to 125	4.11 | 1ku	CDIP (J) | 16	1 | TUBE
SNJ54173W	OBSOLETE	-55 to 125		CFP (W) | 16

SN54173 质量与无铅数据

器件	环保计划*	铅/焊球涂层	MSL 等级/回流焊峰	环保信息与无铅 (Pb-free)	DPPM / MTBF / FIT 率
SN54173J	TBD	A42	N/A for Pkg Type	SN54173J	SN54173J
SNJ54173J	TBD	A42	N/A for Pkg Type	SNJ54173J	SNJ54173J

SN54173 应用技术支持与电子电路设计开发资源下载

1. SN54173 数据资料 dataSheet 下载.PDF
2. TI 德州仪器触发器/锁存器/寄存器产品选型与价格 . xls
3. Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
4. Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
5. TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
6. Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
7. CMOS Power Consumption and CPD Calculation (PDF 89 KB)
8. Designing With Logic (PDF 186 KB)
9. Live Insertion (PDF 150 KB)
10. Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
11. Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
12. HiRel Unitrode Power Management Brochure (PDF 206 KB)
13. LOGIC Pocket Data Book (PDF 6001 KB)
14. HiRel Unitrode Power Management Brochure (PDF 206 KB)
15. Logic Cross-Reference (PDF 2938 KB)