SN54AHCT373 具有三态输出的八路透明 D 类锁存器
The ’AHCT373 devices are octal-transparent D-type latches. When the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is low, the Q outputs are latched at the logic levels of the D inputs.
A buffered output-enable (OE)\ input can be used to place the eight outputs in either a normal logic state (high or low) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components.
OE\ does not affect the internal operations of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state
| SN54AHCT373 | |
| Voltage Nodes(V) | 5 |
| Rating | Military |
SN54AHCT373 特性
- Inputs Are TTL-Voltage Compatible
- Latch-Up Performance Exceeds 250 mA Per JESD 17
- ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)
SN54AHCT373 芯片订购指南
| 器件 | 状态 | 温度 | 价格（美元） | 封装 | 引脚 | 封装数量 | 封装载体 | 丝印标记 |
| SNJ54ABT373FK | ACTIVE | -55 to 125 | 9.75 | 1ku | LCCC (FK) | 20 | 1 | TUBE | |
| SNJ54ABT373J | ACTIVE | -55 to 125 | 5.95 | 1ku | CDIP (J) | 20 | 1 | TUBE | |
| SNJ54ABT373W | ACTIVE | -55 to 125 | 9.75 | 1ku | CFP (W) | 20 | 1 | TUBE |
SN54AHCT373 质量与无铅数据
| 器件 | 环保计划* | 铅/焊球涂层 | MSL 等级/回流焊峰 | 环保信息与无铅 (Pb-free) | DPPM / MTBF / FIT 率 |
| SNJ54ABT373FK | TBD | POST-PLATE | N/A for Pkg Type | SNJ54ABT373FK | SNJ54ABT373FK |
| SNJ54ABT373J | TBD | A42 | N/A for Pkg Type | SNJ54ABT373J | SNJ54ABT373J |
| SNJ54ABT373W | TBD | Call TI | N/A for Pkg Type | SNJ54ABT373W | SNJ54ABT373W |
SN54AHCT373 应用技术支持与电子电路设计开发资源下载
- SN54AHCT373 数据资料 dataSheet 下载.PDF
- TI 德州仪器触发器/锁存器/寄存器产品选型与价格 . xls
- Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
- Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
- TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
- Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
- CMOS Power Consumption and CPD Calculation (PDF 89 KB)
- Designing With Logic (PDF 186 KB)
- Live Insertion (PDF 150 KB)
- Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
- Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- LOGIC Pocket Data Book (PDF 6001 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- Logic Cross-Reference (PDF 2938 KB)
