These 9-bit flip-flops feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing wider buffer registers, I/O ports, bidirectional bus drivers, parity bus interfacing, and working registers.
With the clock-enable () input low, the nine D-type edge-triggered flip-flops enter data on the low-to-high transitions of the clock (CLK) input. Taking high disables the clock buffer, latching the outputs. The ´ALS29823 have noninverting data (D) inputs. Taking the clear () input low causes the nine Q outputs to go low independently of the clock.
A buffered output-enable () input places the nine outputs in either a normal logic state (high or low logic levels) or a high-impedance state
SN54ALS29823 | |
Voltage Nodes(V) | 5 |
Rating | Military |
器件 | 状态 | 温度 | 价格(美元) | 封装 | 引脚 | 封装数量 | 封装载体 | 丝印标记 |
SNJ54ALS29823JT | ACTIVE | -55 to 125 | 5.95 | 1ku | CDIP (J) | 24 | 1 | TUBE |
器件 | 环保计划* | 铅/焊球涂层 | MSL 等级/回流焊峰 | 环保信息与无铅 (Pb-free) | DPPM / MTBF / FIT 率 |
SNJ54ALS29823JT | TBD | A42 | N/A for Pkg Type | SNJ54ALS29823JT | SNJ54ALS29823JT |