SN54AS576 具有三态输出的八路 D 类边沿触发触发器
These octal D-type edge-triggered flip-flops feature 3-state outputs designed specifically for bus driving. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.
These flip-flops enter data on the low-to-high transition of the clock (CLK) input.
The output-enable (
) input does not affect internal operations of the flip-flops. Old data can be retained or new data can be entered while the outputs are disabled.
The SN54ALS576B and SN54AS576 are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS576B, SN74ALS577A, and SN74AS576 are characterized for operation from 0°C to 70°C
| SN54AS576 | |
| Voltage Nodes(V) | 5 |
| Rating | Military |
SN54AS576 特性
- 3-State Buffer-Type Inverting Outputs Drive Bus Lines Directly
- Bus-Structured Pinout
- Buffered Control Inputs
- SN74ALS577A Has Synchronous Clear
- Package Options Include Plastic Small-Outline (DW) Packages, Ceramic Chip Carriers (FK), Standard Plastic (N, NT) and Ceramic (J) 300-mil DIPs, and Ceramic Flat (W) Packages
SN54AS576 芯片订购指南
| 器件 | 状态 | 温度 | 价格（美元） | 封装 | 引脚 | 封装数量 | 封装载体 | 丝印标记 |
| SNJ54AS576FK | ACTIVE | -55 to 125 | 9.75 | 1ku | LCCC (FK) | 20 | 1 | TUBE | |
| SNJ54AS576J | ACTIVE | -55 to 125 | 5.95 | 1ku | CDIP (J) | 20 | 1 | TUBE | |
| SNJ54AS576WD | ACTIVE | -55 to 125 | 10.35 | 1ku | CFP (W) | 20 | 1 | TUBE |
SN54AS576 质量与无铅数据
| 器件 | 环保计划* | 铅/焊球涂层 | MSL 等级/回流焊峰 | 环保信息与无铅 (Pb-free) | DPPM / MTBF / FIT 率 |
| SNJ54AS576FK | TBD | POST-PLATE | N/A for Pkg Type | SNJ54AS576FK | SNJ54AS576FK |
| SNJ54AS576J | TBD | A42 | N/A for Pkg Type | SNJ54AS576J | SNJ54AS576J |
| SNJ54AS576WD | TBD | Call TI | N/A for Pkg Type | SNJ54AS576WD | SNJ54AS576WD |
SN54AS576 应用技术支持与电子电路设计开发资源下载
- SN54AS576 数据资料 dataSheet 下载.PDF
- TI 德州仪器触发器/锁存器/寄存器产品选型与价格 . xls
- Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
- Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
- TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
- Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
- CMOS Power Consumption and CPD Calculation (PDF 89 KB)
- Designing With Logic (PDF 186 KB)
- Live Insertion (PDF 150 KB)
- Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
- Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- LOGIC Pocket Data Book (PDF 6001 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- Logic Cross-Reference (PDF 2938 KB)
