SN54AS821A 具有三态输出的 10 位总线接口触发器
These 10-bit flip-flops feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing wider buffer registers, I/O ports, bidirectional bus drivers with parity, and working registers.
The ten flip-flops are edge-triggered D-type flip-flops. On the positive transition of the clock (CLK) input, the Q outputs are true to the data (D) input.
A buffered output-enable (
) input can be used to place the ten outputs in either a normal logic state (high or low logic levels) or a high-
impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components
| SN54AS821A | |
| Voltage Nodes(V) | 5 |
| Rating | Military |
SN54AS821A 特性
- Functionally Equivalent to AMD's AM29821
- Provide Extra Data Width Necessary for Wider Address/Data Paths or Buses With Parity
- Outputs Have Undershoot-Protection Circuitry
- Power-Up High-Impedance State
- Buffered Control Inputs to Reduce dc Loading Effects
- Package Options Include Plastic Small-Outline (DW) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (NT) and Ceramic (JT) 300-mil DIPs
SN54AS821A 芯片订购指南
| 器件 | 状态 | 温度 | 价格（美元） | 封装 | 引脚 | 封装数量 | 封装载体 | 丝印标记 |
| SNJ54AS821AFK | ACTIVE | -55 to 125 | 9.75 | 1ku | LCCC (FK) | 28 | 1 | TUBE | |
| SNJ54AS821AJ | ACTIVE | -55 to 125 | 5.95 | 1ku | CDIP (J) | 24 | 1 | TUBE | |
| SNJ54AS821AWD | ACTIVE | -55 to 125 | 10.35 | 1ku | CFP (W) | 24 | 1 | TUBE |
SN54AS821A 质量与无铅数据
| 器件 | 环保计划* | 铅/焊球涂层 | MSL 等级/回流焊峰 | 环保信息与无铅 (Pb-free) | DPPM / MTBF / FIT 率 |
| SNJ54AS821AFK | TBD | POST-PLATE | N/A for Pkg Type | SNJ54AS821AFK | SNJ54AS821AFK |
| SNJ54AS821AJ | TBD | A42 | N/A for Pkg Type | SNJ54AS821AJ | SNJ54AS821AJ |
| SNJ54AS821AWD | TBD | Call TI | N/A for Pkg Type | SNJ54AS821AWD | SNJ54AS821AWD |
SN54AS821A 应用技术支持与电子电路设计开发资源下载
- SN54AS821A 数据资料 dataSheet 下载.PDF
- TI 德州仪器触发器/锁存器/寄存器产品选型与价格 . xls
- Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
- Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
- TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
- Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
- CMOS Power Consumption and CPD Calculation (PDF 89 KB)
- Designing With Logic (PDF 186 KB)
- Live Insertion (PDF 150 KB)
- Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
- Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- LOGIC Pocket Data Book (PDF 6001 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- Logic Cross-Reference (PDF 2938 KB)
