SN54HC165 并联负载 8 位移位寄存器
The ’HC165 devices are 8-bit parallel-load shift registers that, when clocked, shift the data toward a serial (QH) output. Parallel-in access to each stage is provided by eight individual direct data (A-H) inputs that are enabled by a low level at the shift/load (SH/LD) input. The ’HC165 devices also feature a clock-inhibit (CLK INH) function and a complementary serial (QH) output.
Clocking is accomplished by a low-to-high transition of the clock (CLK) input while SH/LD is held high and CLK INH is held low. The functions of CLK and CLK INH are interchangeable. Since a low CLK and a low-to-high transition of CLK INH also accomplish clocking, CLK INH should be changed to the high level only while CLK is high
| SN54HC165 | |
| Technology Family | HC |
| Rating | Military |
SN54HC165 特性
- Wide Operating Voltage Range of 2 V to 6 V
- Outputs Can Drive Up To 10 LSTTL Loads
- Low Power Consumption, 80-µA Max ICC
- Typical tpd = 13 ns
- ±4-mA Output Drive at 5 V
- Low Input Current of 1 µA Max
- Complementary Outputs
- Direct Overriding Load (Data) Inputs
- Gated Clock Inputs
- Parallel-to-Serial Data Conversion
SN54HC165 芯片订购指南
| 器件 | 状态 | 温度 | 价格 | 封装 | 引脚 | 封装数量 | 封装载体 | 丝印标记 |
| SN54HC165J | ACTIVE | -55 to 125 | 16.23 | 1ku | CDIP (J) | 16 | 1 | TUBE | |
| SNJ54HC165FK | ACTIVE | -55 to 125 | 17.37 | 1ku | LCCC (FK) | 20 | 1 | TUBE | |
| SNJ54HC165J | ACTIVE | -55 to 125 | 23.81 | 1ku | CDIP (J) | 16 | 1 | TUBE | |
| SNJ54HC165W | ACTIVE | -55 to 125 | 16.23 | 1ku | CFP (W) | 16 | 1 | TUBE |
SN54HC165 质量与无铅数据
| 器件 | 环保计划* | 铅/焊球涂层 | MSL 等级/回流焊峰 | 环保信息与无铅 (Pb-free) | DPPM / MTBF / FIT 率 |
| SN54HC165J | TBD | A42 | N/A for Pkg Type | SN54HC165J | SN54HC165J |
| SNJ54HC165FK | TBD | POST-PLATE | N/A for Pkg Type | SNJ54HC165FK | SNJ54HC165FK |
| SNJ54HC165J | TBD | A42 | N/A for Pkg Type | SNJ54HC165J | SNJ54HC165J |
| SNJ54HC165W | TBD | Call TI | N/A for Pkg Type | SNJ54HC165W | SNJ54HC165W |
SN54HC165 应用技术支持与电子电路设计开发资源下载
- SN54HC165 数据资料 dataSheet 下载.PDF
- TI 德州仪器触发器/锁存器/寄存器产品选型与价格 . xls
- Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
- Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
- TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
- Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
- CMOS Power Consumption and CPD Calculation (PDF 89 KB)
- Designing With Logic (PDF 186 KB)
- Live Insertion (PDF 150 KB)
- Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
- Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- LOGIC Pocket Data Book (PDF 6001 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- Logic Cross-Reference (PDF 2938 KB)
