SN54LS165A 并联负载 8 位移位寄存器
The ’165 and ’LS165A are 8-bit serial shift registers that shift the data in the direction of QA toward QH when clocked. Parallel-in access to each stage is made available by eight individual, direct data inputs that are enabled by a low level at the shift/load (SH/LD\) input. These registers also feature gated clock (CLK) inputs and complementary outputs from the eighth bit. All inputs are diode-clamped to minimize transmission-line effects, thereby simplifying system design.
Clocking is accomplished through a two-input positive-NOR gate, permitting one input to be used as a clock-inhibit function. Holding either of the clock inputs high inhibits clocking, and holding either clock input low with SH/LD\ high enables the other clock input.
| SN54LS165A | |
| Technology Family | LS |
| Rating | Military |
SN54LS165A 特性
- Complementary Outputs
- Direct Overriding Load (Data) Inputs
- Gated Clock Inputs
- Parallel-to-Serial Data Conversion
SN54LS165A 芯片订购指南
| 器件 | 状态 | 温度 | 价格 | 封装 | 引脚 | 封装数量 | 封装载体 | 丝印标记 |
| SN54LS165AJ | ACTIVE | -55 to 125 | 16.23 | 1ku | CDIP (J) | 16 | 1 | TUBE | |
| SNJ54LS165AFK | ACTIVE | -55 to 125 | 17.37 | 1ku | LCCC (FK) | 20 | 1 | TUBE | |
| SNJ54LS165AJ | ACTIVE | -55 to 125 | 23.81 | 1ku | CDIP (J) | 16 | 1 | TUBE | |
| SNJ54LS165AW | ACTIVE | -55 to 125 | 16.23 | 1ku | CFP (W) | 16 | 1 | TUBE |
SN54LS165A 质量与无铅数据
| 器件 | 环保计划* | 铅/焊球涂层 | MSL 等级/回流焊峰 | 环保信息与无铅 (Pb-free) | DPPM / MTBF / FIT 率 |
| SN54LS165AJ | TBD | A42 | N/A for Pkg Type | SN54LS165AJ | SN54LS165AJ |
| SNJ54LS165AFK | TBD | POST-PLATE | N/A for Pkg Type | SNJ54LS165AFK | SNJ54LS165AFK |
| SNJ54LS165AJ | TBD | A42 | N/A for Pkg Type | SNJ54LS165AJ | SNJ54LS165AJ |
| SNJ54LS165AW | TBD | Call TI | N/A for Pkg Type | SNJ54LS165AW | SNJ54LS165AW |
SN54LS165A 应用技术支持与电子电路设计开发资源下载
- SN54LS165A 数据资料 dataSheet 下载.PDF
- TI 德州仪器触发器/锁存器/寄存器产品选型与价格 . xls
- Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
- Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
- TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
- Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
- CMOS Power Consumption and CPD Calculation (PDF 89 KB)
- Designing With Logic (PDF 186 KB)
- Live Insertion (PDF 150 KB)
- Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
- Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- LOGIC Pocket Data Book (PDF 6001 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- Logic Cross-Reference (PDF 2938 KB)
