SN54LS373-SP 具有三态输出的八路透明 D 类锁存器
These 8-bit registers feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. The high-impedance 3-state and increased high-logic-level drive provide these registers with the capability of being connected directly to and driving the bus lines in a bus-organized system without need for interface or pullup components. These devices are particularly attractive for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.
The eight latches of the ’LS373 and ’S373 are transparent D-type latches, meaning that while the enable (C or CLK) input is high, the Q outputs follow the data (D) inputs. When C or CLK is taken low, the output is latched at the level of the data that was set up.
| SN54LS373-SP | |
| Voltage Nodes(V) | 6, 5, 2 |
| Rating | Space |
SN54LS373-SP 特性
- Choice of Eight Latches or Eight D-Type Flip-Flops in a Single Package
- 3-State Bus-Driving Outputs
- Full Parallel Access for Loading
- Buffered Control Inputs
- Clock-Enable Input Has Hysteresis to Improve Noise Rejection (’S373 and ’S374)
- P-N-P Inputs Reduce DC Loading on Data Lines (’S373 and ’S374)
SN54LS373-SP 芯片订购指南
| 器件 | 状态 | 温度 | 价格（美元） | 封装 | 引脚 | 封装数量 | 封装载体 | 丝印标记 |
| JM38510/32502SRA | ACTIVE | 5962-9074601MRA | 12.02 | 1ku | CDIP (J) | 20 | 1 | TUBE | |
| JM38510/32502SSA | ACTIVE | 5962-9074601MSA | 13.44 | 1ku | CFP (W) | 20 | 1 | TUBE |
SN54LS373-SP 质量与无铅数据
| 器件 | 环保计划* | 铅/焊球涂层 | MSL 等级/回流焊峰 | 环保信息与无铅 (Pb-free) | DPPM / MTBF / FIT 率 |
| JM38510/32502SRA | TBD | A42 | N/A for Pkg Type | JM38510/32502SRA | JM38510/32502SRA |
| JM38510/32502SSA | TBD | Call TI | N/A for Pkg Type | JM38510/32502SSA | JM38510/32502SSA |
SN54LS373-SP 应用技术支持与电子电路设计开发资源下载
- SN54LS373-SP 数据资料 dataSheet 下载.PDF
- TI 德州仪器触发器/锁存器/寄存器产品选型与价格 . xls
- Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
- Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
- TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
- Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
- CMOS Power Consumption and CPD Calculation (PDF 89 KB)
- Designing With Logic (PDF 186 KB)
- Live Insertion (PDF 150 KB)
- Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
- Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- LOGIC Pocket Data Book (PDF 6001 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- Logic Cross-Reference (PDF 2938 KB)
