These devices each contain an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. The storage register has parallel 3-state ('LS595) or open-collector ('LS596) outputs. Separate clocks are provided for both the shift register and the storage register. The shift register has a direct-overriding clear, serial input, and serial output pins for cascading.
Both the shift register and storage register clocks are positive-edge triggered. If the user wishes to connect both clocks together, the shift register state will always be one clock pulse ahead of the storage register
SN54LS595 | |
Technology Family | LS |
Rating | Military |
器件 | 状态 | 温度 | 价格 | 封装 | 引脚 | 封装数量 | 封装载体 | 丝印标记 |
SN54LS595J | ACTIVE | -55 to 125 | 16.23 | 1ku | CDIP (J) | 16 | 1 | TUBE | |
SNJ54LS595FK | ACTIVE | -55 to 125 | 17.37 | 1ku | LCCC (FK) | 20 | 1 | TUBE | |
SNJ54LS595J | ACTIVE | -55 to 125 | 23.81 | 1ku | CDIP (J) | 16 | 1 | TUBE | |
SNJ54LS595W | ACTIVE | -55 to 125 | 16.23 | 1ku | CFP (W) | 16 | 1 | TUBE |
器件 | 环保计划* | 铅/焊球涂层 | MSL 等级/回流焊峰 | 环保信息与无铅 (Pb-free) | DPPM / MTBF / FIT 率 |
SN54LS595J | TBD | A42 | N/A for Pkg Type | SN54LS595J | SN54LS595J |
SNJ54LS595FK | TBD | POST-PLATE | N/A for Pkg Type | SNJ54LS595FK | SNJ54LS595FK |
SNJ54LS595J | TBD | A42 | N/A for Pkg Type | SNJ54LS595J | SNJ54LS595J |
SNJ54LS595W | TBD | Call TI | N/A for Pkg Type | SNJ54LS595W | SNJ54LS595W |