SN54LS674 16 位移位寄存器
The 'LS673 is a 16-bit shift register and a 16-bit storage register in a single 24-pin package. A three-state input/output (SER/Q15) port to the shift register allows serial entry and/or reading of data. The storage register is connected in a parallel data loop with the shift register and may be asynchronously cleared by taking the store-clear input low. The storage register may be parallel loaded with shift-register data to provide shift-register status via the parallel outputs. The shift register can be parallel loaded with the storage-register data upon commmand.
A high logic level at the chip-level (CS\) input disables both the shift-register clock and the storage register clock and places SER/Q15 in the high-impedance state
| SN54LS674 | |
| Technology Family | LS |
| Rating | Military |
SN54LS674 特性
- 'LS673
- 16-Bit Serial-In, Serial-Out Shift Register with 16-Bit Parallel-Out Storage Register
- Performs Serial-to-Parallel Conversion
- 'LS674
- 16-Bit Parallel-In, Serial-Out Shift Register
- Performs Parallel-to-Serial Conversion
SN54LS674 芯片订购指南
| 器件 | 状态 | 温度 | 价格 | 封装 | 引脚 | 封装数量 | 封装载体 | 丝印标记 |
| SN54LS674J | ACTIVE | -55 to 125 | 16.23 | 1ku | CDIP (J) | 24 | 1 | TUBE | |
| SNJ54LS674FK | ACTIVE | -55 to 125 | 17.37 | 1ku | LCCC (FK) | 28 | 1 | TUBE | |
| SNJ54LS674J | ACTIVE | -55 to 125 | 23.81 | 1ku | CDIP (J) | 24 | 1 | TUBE | |
| SNJ54LS674W | ACTIVE | -55 to 125 | 16.23 | 1ku | CFP (W) | 24 | 1 | TUBE |
SN54LS674 质量与无铅数据
| 器件 | 环保计划* | 铅/焊球涂层 | MSL 等级/回流焊峰 | 环保信息与无铅 (Pb-free) | DPPM / MTBF / FIT 率 |
| SN54LS674J | TBD | A42 | N/A for Pkg Type | SN54LS674J | SN54LS674J |
| SNJ54LS674FK | TBD | POST-PLATE | N/A for Pkg Type | SNJ54LS674FK | SNJ54LS674FK |
| SNJ54LS674J | TBD | A42 | N/A for Pkg Type | SNJ54LS674J | SNJ54LS674J |
| SNJ54LS674W | TBD | Call TI | N/A for Pkg Type | SNJ54LS674W | SNJ54LS674W |
SN54LS674 应用技术支持与电子电路设计开发资源下载
- SN54LS674 数据资料 dataSheet 下载.PDF
- TI 德州仪器触发器/锁存器/寄存器产品选型与价格 . xls
- Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
- Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
- TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
- Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
- CMOS Power Consumption and CPD Calculation (PDF 89 KB)
- Designing With Logic (PDF 186 KB)
- Live Insertion (PDF 150 KB)
- Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
- Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- LOGIC Pocket Data Book (PDF 6001 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- Logic Cross-Reference (PDF 2938 KB)
