SN54LVC32A 四路 2 输入正或门

The SN54LVC32A quadruple 2-input positive-OR gate is designed for 2.7-V to 3.6-V VCC operation, and the SN74LVC32A quadruple 2-input positive-OR gate is designed for 1.65-V to 3.6-V VCC operation.

The ’LVC32A devices perform the Boolean function Y = A + B or Y = (A\ • B\)\ in positive logic.

Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators in a mixed 3.3-V/5-V system environment

SN54LVC32A
Rating Military  
Technology Family LVC  
SN54LVC32A 特性
SN54LVC32A 芯片订购指南
器件 状态 温度 价格 封装 | 引脚 封装数量 | 封装载体 丝印标记
SNJ54LVC32AFK ACTIVE -55 to 125 12.28 | 1ku LCCC (FK) | 20 1 | TUBE  
SNJ54LVC32AJ ACTIVE -55 to 125 4.37 | 1ku CDIP (J) | 14 1 | TUBE  
SNJ54LVC32AW ACTIVE -55 to 125 12.28 | 1ku CFP (W) | 14 1 | TUBE  
SN54LVC32A 质量与无铅数据
器件 环保计划* 铅/焊球涂层 MSL 等级/回流焊峰 环保信息与无铅 (Pb-free) DPPM / MTBF / FIT 率
SNJ54LVC32AFK TBD  POST-PLATE  N/A for Pkg Type SNJ54LVC32AFK SNJ54LVC32AFK
SNJ54LVC32AJ TBD  A42   N/A for Pkg Type SNJ54LVC32AJ SNJ54LVC32AJ
SNJ54LVC32AW TBD  A42   N/A for Pkg Type SNJ54LVC32AW SNJ54LVC32AW
SN54LVC32A 应用技术支持与电子电路设计开发资源下载
  1. SN54LVC32A 数据资料 dataSheet 下载.PDF
  2. TI 德州仪器门电路产品选型与价格 . xls
  3. Logic Guide 2009 (PDF 4263 KB)
  4. Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
  5. Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
  6. TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
  7. Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
  8. CMOS Power Consumption and CPD Calculation (PDF 89 KB)
  9. Designing With Logic (PDF 186 KB)
  10. Live Insertion (PDF 150 KB)
  11. Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
  12. Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
  13. HiRel Unitrode Power Management Brochure (PDF 206 KB)
  14. LOGIC Pocket Data Book (PDF 6001 KB)
  15. HiRel Unitrode Power Management Brochure (PDF 206 KB)
  16. Logic Cross-Reference (PDF 2938 KB)