SN54LVCH244A-SP 具有三态输出的八路缓冲器/驱动器
The SN54LVCH244A octal buffer/line driver is designed for 2.7-V to 3.6-V VCC operation, and the SN74LVCH244A octal buffer/line driver is designed for 1.65-V to 3.6-V VCC operation.
These devices are organized as two 4-bit line drivers with separate output-enable (OE) inputs. When OE is low, these devices pass data from the A inputs to the Y outputs. When OE is high, the outputs are in the high-impedance state.
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators in a mixed 3.3-V/5-V system environment.
These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver
| SN54LVCH244A-SP | |
| Voltage Nodes (V) | 3.3, 2.7, 2.5, 1.8 |
| Vcc range (V) | 2.0 to 3.6 |
| Logic | True |
| Input Level | TTL/CMOS |
| Output Level | LVTTL |
| No. of Outputs | 8 |
| Rating | Space |
| Technology Family | LVC |
SN54LVCH244A-SP 特性
- Operate From 1.65 V to 3.6 V
- Inputs Accept Voltages to 5.5 V
- Max tpd of 5.9 ns at 3.3 V
- Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C
- Typical VOHV (Output VOH Undershoot) >2 V at VCC = 3.3 V, TA = 25°C
- Support Mixed-Mode Signal Operation on All Ports (5-V Input/Output Voltage With 3.3-V VCC)
- Ioff Supports Partial-Power-Down Mode Operation
- Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
- Latch-Up Performance Exceeds 250 mA Per JESD 17
- ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)
SN54LVCH244A-SP 芯片订购指南
| 器件 | 状态 | 温度 | 价格（美元） | 封装 | 引脚 | 封装数量 | 封装载体 | 丝印标记 |
| 5962-9754201V2A | ACTIVE | -55 to 125 | 142.95 | 100u | LCCC (FK) | 20 | 1 | TUBE | |
| 5962-9754201VRA | ACTIVE | -55 to 125 | 137.90 | 100u | CDIP (J) | 20 | 1 | TUBE | |
| 5962-9754201VSA | ACTIVE | -55 to 125 | 179.00 | 100u | CFP (W) | 20 | 1 | TUBE |
SN54LVCH244A-SP 质量与无铅数据
| 器件 | 环保计划* | 铅/焊球涂层 | MSL 等级/回流焊峰 | 环保信息与无铅 (Pb-free) | DPPM / MTBF / FIT 率 |
| 5962-9754201V2A | TBD | POST-PLATE | N/A for Pkg Type | 5962-9754201V2A | 5962-9754201V2A |
| 5962-9754201VRA | TBD | A42 | N/A for Pkg Type | 5962-9754201VRA | 5962-9754201VRA |
| 5962-9754201VSA | TBD | Call TI | N/A for Pkg Type | 5962-9754201VSA | 5962-9754201VSA |
SN54LVCH244A-SP 应用技术支持与电子电路设计开发资源下载
- SN54LVCH244A-SP 数据资料 dataSheet 下载.PDF
- TI 德州仪器触发器/锁存器/寄存器产品选型与价格 . xls
- Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
- Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
- TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
- Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
- CMOS Power Consumption and CPD Calculation (PDF 89 KB)
- Designing With Logic (PDF 186 KB)
- Live Insertion (PDF 150 KB)
- Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
- Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- LOGIC Pocket Data Book (PDF 6001 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- Logic Cross-Reference (PDF 2938 KB)
