CD74AC573 具有三态输出的八进制透明同向锁存器
The RCA-CD54/74AC563 and CD54/74AC573 and the CD54/74ACT563 and CD54/74ACT573 octal transparent 3-state latches use the RCA ADVANCED CMOS technology. The outputs are transparent to the inputs when the Latch Enable (LE\) is HIGH. When the Latch Enable (LE\) goes LOW, the data is latched. The Output Enable (OE\) controls the 3-state ouputs. When the Output Enable (OE\) is HIGH, the outputs are in the high-impendance state. The latch operation is independent of the state of the Output Enable.
The CD74AC/ACT563 and CD74AC/ACT573 are supplied in 20-lead dual-in-line plastic packages (E suffix) and in 20-lead dual-in-line small-outline plastic packages (M suffix). Both package types are operable over the folowing temperature ranges: Commerical (0 to 70°C); Industrial (-40 to +85°C); and Extended Industrial/Military (-55 to +125°C).
|
CD74AC573 |
| Technology Family |
AC |
| Rating |
Catalog |
CD74AC573 特性
- Buffered inputs
- Typical propagation delay:
4.3 ns @ VCC = 5 V, TA = 25°C, CL = 50 pf
- Exceeds 2-kV ESD Protection - MIL-STD-883, Method 3015
- SCR-Latchup-resistant CMOS process and circuit design
- Speed of bipolar FAST*/AS/D with significantly reduced power consumption
- Balanced propagation delays
- AC types feature 1.5-V to 5.5-V operation and balanced noise immunity at 30% of the supply
- ±24-mA output drive current
-Fanout to 15 FAST* ICs
-Drives 50-ohm transmission lines
- Characterized for operation from –40° to 85°C
CD74AC573 芯片订购指南
| 器件 |
状态 |
温度 |
价格（美元） |
封装 | 引脚 |
封装数量 | 封装载体 |
丝印标记 |
| CD74AC573E |
ACTIVE |
-55 to 125 |
0.60 | 1ku |
PDIP (N) | 20 |
20 | TUBE |
|
| CD74AC573EE4 |
ACTIVE |
-55 to 125 |
0.60 | 1ku |
PDIP (N) | 20 |
20 | TUBE |
|
| CD74AC573M |
ACTIVE |
-55 to 125 |
0.65 | 1ku |
SOIC (DW) | 20 |
25 | TUBE |
|
| CD74AC573M96 |
ACTIVE |
-55 to 125 |
0.55 | 1ku |
SOIC (DW) | 20 |
2000 | LARGE T&R |
|
| CD74AC573M96E4 |
ACTIVE |
-55 to 125 |
0.55 | 1ku |
SOIC (DW) | 20 |
2000 | LARGE T&R |
|
| CD74AC573M96G4 |
ACTIVE |
-55 to 125 |
0.55 | 1ku |
SOIC (DW) | 20 |
2000 | LARGE T&R |
|
| CD74AC573ME4 |
ACTIVE |
-55 to 125 |
0.65 | 1ku |
SOIC (DW) | 20 |
25 | TUBE |
|
| CD74AC573MG4 |
ACTIVE |
-55 to 125 |
0.65 | 1ku |
SOIC (DW) | 20 |
25 | TUBE |
|
CD74AC573 质量与无铅数据
| 器件 |
环保计划* |
铅/焊球涂层 |
MSL 等级/回流焊峰 |
环保信息与无铅 (Pb-free) |
DPPM / MTBF / FIT 率 |
| CD74AC573E |
Pb-Free (RoHS) |
CU NIPDAU |
N/A for Pkg Type |
CD74AC573E |
CD74AC573E |
| CD74AC573EE4 |
Pb-Free (RoHS) |
CU NIPDAU |
N/A for Pkg Type |
CD74AC573EE4 |
CD74AC573EE4 |
| CD74AC573M |
Green (RoHS & no Sb/Br) |
CU NIPDAU |
Level-1-260C-UNLIM |
CD74AC573M |
CD74AC573M |
| CD74AC573M96 |
Green (RoHS & no Sb/Br) |
CU NIPDAU |
Level-1-260C-UNLIM |
CD74AC573M96 |
CD74AC573M96 |
| CD74AC573M96E4 |
Green (RoHS & no Sb/Br) |
CU NIPDAU |
Level-1-260C-UNLIM |
CD74AC573M96E4 |
CD74AC573M96E4 |
| CD74AC573M96G4 |
Green (RoHS & no Sb/Br) |
CU NIPDAU |
Level-1-260C-UNLIM |
CD74AC573M96G4 |
CD74AC573M96G4 |
| CD74AC573ME4 |
Green (RoHS & no Sb/Br) |
CU NIPDAU |
Level-1-260C-UNLIM |
CD74AC573ME4 |
CD74AC573ME4 |
| CD74AC573MG4 |
Green (RoHS & no Sb/Br) |
CU NIPDAU |
Level-1-260C-UNLIM |
CD74AC573MG4 |
CD74AC573MG4 |
CD74AC573 应用技术支持与电子电路设计开发资源下载
- CD74AC573 数据资料 dataSheet 下载.PDF
- TI 德州仪器触发器/锁存器/寄存器产品选型与价格 . xls
- Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
- Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
- TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
- Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
- CMOS Power Consumption and CPD Calculation (PDF 89 KB)
- Designing With Logic (PDF 186 KB)
- Live Insertion (PDF 150 KB)
- Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
- Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- LOGIC Pocket Data Book (PDF 6001 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- Logic Cross-Reference (PDF 2938 KB)
