CD74HCT670 高速 CMOS 逻辑 4 x 4 寄存器文件
The ’HCT670 and CD74HCT670 are 16-bit register files organized as 4 words x 4 bits each. Read and write address and enable inputs allow simultaneous writing into one location while reading another. Four data inputs are provided to store the 4-bit word. The write address inputs (WA0 and WA1) determine the location of the stored word in the register. When write enable (WE\) is low the word is entered into the address location and it remains transparent to the data. The outputs will reflect the true form of the input data. When (WE\) is high data and address inputs are inhibited. Data acquisition from the four registers is made possible by the read address inputs (RA1 and RA0). The addressed word appears at the output when the read enable (RE\) is low.
| CD74HCT670 | |
| Rating | Military |
| Technology Family | HCT |
CD74HCT670 特性
- Simultaneous and Independent Read and Write Operations
- Expandable to 512 Words of n-Bits
- Three-State Outputs
- Organized as 4 Words x 4 Bits Wide
- Buffered Inputs
- Typical Read Time = 16ns for ’HCT670 VCC = 5V, CL = 15pF, TA = 25°C
- Fanout (Over Temperature Range)
- Standard Outputs...10 LSTTL Loads
- Bus Driver Outputs...15 LSTTL Loads
- Wide Operating Temperature Range... –55°C to 125°C
- Balanced Propagation Delay and Transition Times
- Significant Power Reduction Compared to LSTTL Logic ICs
- HC Types
- 2V to 6V Operation
- High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V
- HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility, VIL = 0.8V (Max), VIH = 2V (Min)
- CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH
CD74HCT670 芯片订购指南
| 器件 | 状态 | 温度 | 价格 | 封装 | 引脚 | 封装数量 | 封装载体 | 丝印标记 |
| CD74HCT670E | ACTIVE | -55 to 125 | 0.46 | 1ku | PDIP (N) | 16 | 25 | TUBE | CD74HCT670E |
| CD74HCT670EE4 | ACTIVE | -55 to 125 | 0.46 | 1ku | PDIP (N) | 16 | 25 | TUBE | CD74HCT670E |
| CD74HCT670M | ACTIVE | -55 to 125 | 0.50 | 1ku | SOIC (D) | 16 | 40 | TUBE | HCT670M |
| CD74HCT670ME4 | ACTIVE | -55 to 125 | 0.50 | 1ku | SOIC (D) | 16 | 40 | TUBE | HCT670M |
| CD74HCT670MG4 | ACTIVE | -55 to 125 | 0.50 | 1ku | SOIC (D) | 16 | 40 | TUBE | HCT670M |
CD74HCT670 质量与无铅数据
| 器件 | 环保计划* | 铅/焊球涂层 | MSL 等级/回流焊峰 | 环保信息与无铅 (Pb-free) | DPPM / MTBF / FIT 率 |
| CD74HCT670E | Pb-Free (RoHS) | CU NIPDAU | N/A for Pkg Type | CD74HCT670E | CD74HCT670E |
| CD74HCT670EE4 | Pb-Free (RoHS) | CU NIPDAU | N/A for Pkg Type | CD74HCT670EE4 | CD74HCT670EE4 |
| CD74HCT670M | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | CD74HCT670M | CD74HCT670M |
| CD74HCT670ME4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | CD74HCT670ME4 | CD74HCT670ME4 |
| CD74HCT670MG4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | CD74HCT670MG4 | CD74HCT670MG4 |
CD74HCT670 应用技术支持与电子电路设计开发资源下载
- CD74HCT670 数据资料 dataSheet 下载.PDF
- TI 德州仪器触发器/锁存器/寄存器产品选型与价格 . xls
- Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
- Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
- TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
- Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
- CMOS Power Consumption and CPD Calculation (PDF 89 KB)
- Designing With Logic (PDF 186 KB)
- Live Insertion (PDF 150 KB)
- Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
- Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- LOGIC Pocket Data Book (PDF 6001 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- Logic Cross-Reference (PDF 2938 KB)
