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CY74FCT162373AT 具有三态输出的 16 位透明 D 类锁存器

CY74FCT16373T and CY74FCT162373T are 16-bit D-type latches designed for use in bus applications requiring high speed and low power. These devices can be used as two independent 8-bit latches or as a single 16-bit latch by connecting the Output Enable (OE\) and Latch (LE) inputs. Flow-through pinout and small shrink packaging aid in simplifying board layout.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

The CY74FCT16373T is ideally suited for driving high-capacitance loads and low-impedance backplanes.

The CY74FCT162373T has 24-mA balanced output drivers with current limiting resistors in the outputs

	CY74FCT162373AT
Voltage Nodes(V)	5
Rating	Catalog

CY74FCT162373AT 特性

• Ioff supports partial-power-down mode operation
• Edge-rate control circuitry for significantly improved noise characteristics
• Typical output skew < 250 ps
• ESD > 2000V
• TSSOP (19.6-mil pitch) and SSOP (25-mil pitch) packages
• Industrial temperature range of -40°C to +85°C
• VCC = 5V ± 10%
• CY74FCT16373T Features:
  • 64 mA sink current, 32 mA source current
  • Typical VOLP (ground bounce) <1.0V at VCC = 5V, TA = 25°C
• CY74FCT162373T Features:
  • Balanced 24 mA output drivers
  • Reduced system switching noise
  • Typical VOLP (ground bounce) >0.6V at VCC = 5V, TA = 25°C

CY74FCT162373AT 芯片订购指南

器件	状态	温度	价格（美元）	封装 | 引脚	封装数量 | 封装载体	丝印标记
CY74FCT162373ATPVC	ACTIVE	-40 to 85	1.40 | 1ku	SSOP (DL) | 48	25 | TUBE

CY74FCT162373AT 质量与无铅数据

器件	环保计划*	铅/焊球涂层	MSL 等级/回流焊峰	环保信息与无铅 (Pb-free)	DPPM / MTBF / FIT 率
CY74FCT162373ATPVC	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-1-260C-UNLIM	CY74FCT162373ATPVC	CY74FCT162373ATPVC

CY74FCT162373AT 应用技术支持与电子电路设计开发资源下载

1. CY74FCT162373AT 数据资料 dataSheet 下载.PDF
2. TI 德州仪器触发器/锁存器/寄存器产品选型与价格 . xls
3. Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
4. Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
5. TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
6. Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
7. CMOS Power Consumption and CPD Calculation (PDF 89 KB)
8. Designing With Logic (PDF 186 KB)
9. Live Insertion (PDF 150 KB)
10. Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
11. Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
12. HiRel Unitrode Power Management Brochure (PDF 206 KB)
13. LOGIC Pocket Data Book (PDF 6001 KB)
14. HiRel Unitrode Power Management Brochure (PDF 206 KB)
15. Logic Cross-Reference (PDF 2938 KB)