SN74ALS109A 具有清零和预设功能的双路 J-K 上升沿触发器
These devices contain two independent J-K\ positive-edge-triggered flip-flops. A low level at the preset (
) or clear (
) inputs sets or resets the outputs regardless of the levels of the other inputs. When and are inactive (high), data at the J and K\ inputs meeting the setup-time requirements are transferred to the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the J and K\ inputs can be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops by grounding K\ and tying J high
| SN74ALS109A | |
| Voltage Nodes(V) | 5 |
| Vcc range(V) | 4.5 to 5.5 |
| Input Level | TTL |
| Output Level | TTL |
| Output Drive(mA) | -0.4/8 |
| Output | 2S |
| No. of Bits | 2 |
| th(ns) | 0 |
| tpd max(ns) | 18 |
| tsu(ns) | 15 |
| Technology Family | ALS |
| Rating | Catalog |
SN74ALS109A 特性
- Package Options Include Plastic Small-Outline (D) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs
SN74ALS109A 芯片订购指南
| 器件 | 状态 | 温度 | 价格 | 封装 | 引脚 | 封装数量 | 封装载体 | 丝印标记 |
| SN74ALS109AD | ACTIVE | 0 to 70 | 0.90 | 1ku | SOIC (D) | 16 | 40 | TUBE | ALS109A |
| SN74ALS109ADE4 | ACTIVE | 0 to 70 | 0.90 | 1ku | SOIC (D) | 16 | 40 | TUBE | ALS109A |
| SN74ALS109ADG4 | ACTIVE | 0 to 70 | 0.90 | 1ku | SOIC (D) | 16 | 40 | TUBE | ALS109A |
| SN74ALS109ADR | ACTIVE | 0 to 70 | 0.75 | 1ku | SOIC (D) | 16 | 2500 | LARGE T&R | ALS109A |
| SN74ALS109ADRE4 | ACTIVE | 0 to 70 | 0.75 | 1ku | SOIC (D) | 16 | 2500 | LARGE T&R | ALS109A |
| SN74ALS109ADRG4 | ACTIVE | 0 to 70 | 0.75 | 1ku | SOIC (D) | 16 | 2500 | LARGE T&R | ALS109A |
| SN74ALS109AN | ACTIVE | 0 to 70 | 0.85 | 1ku | PDIP (N) | 16 | 25 | TUBE | SN74ALS109AN |
| SN74ALS109AN3 | OBSOLETE | 0 to 70 | PDIP (N) | 16 | |||
| SN74ALS109ANE4 | ACTIVE | 0 to 70 | 0.85 | 1ku | PDIP (N) | 16 | 25 | TUBE | SN74ALS109AN |
| SN74ALS109ANSR | ACTIVE | 0 to 70 | 0.85 | 1ku | SO (NS) | 16 | 2000 | LARGE T&R | ALS109A |
| SN74ALS109ANSRE4 | ACTIVE | 0 to 70 | 0.85 | 1ku | SO (NS) | 16 | 2000 | LARGE T&R | ALS109A |
| SN74ALS109ANSRG4 | ACTIVE | 0 to 70 | 0.85 | 1ku | SO (NS) | 16 | 2000 | LARGE T&R | ALS109A |
SN74ALS109A 质量与无铅数据
| 器件 | 环保计划* | 铅/焊球涂层 | MSL 等级/回流焊峰 | 环保信息与无铅 (Pb-free) | DPPM / MTBF / FIT 率 |
| SN74ALS109AD | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74ALS109AD | SN74ALS109AD |
| SN74ALS109ADE4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74ALS109ADE4 | SN74ALS109ADE4 |
| SN74ALS109ADG4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74ALS109ADG4 | SN74ALS109ADG4 |
| SN74ALS109ADR | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74ALS109ADR | SN74ALS109ADR |
| SN74ALS109ADRE4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74ALS109ADRE4 | SN74ALS109ADRE4 |
| SN74ALS109ADRG4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74ALS109ADRG4 | SN74ALS109ADRG4 |
| SN74ALS109AN | Pb-Free (RoHS) | CU NIPDAU | N/A for Pkg Type | SN74ALS109AN | SN74ALS109AN |
| SN74ALS109ANE4 | Pb-Free (RoHS) | CU NIPDAU | N/A for Pkg Type | SN74ALS109ANE4 | SN74ALS109ANE4 |
| SN74ALS109ANSR | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74ALS109ANSR | SN74ALS109ANSR |
| SN74ALS109ANSRE4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74ALS109ANSRE4 | SN74ALS109ANSRE4 |
| SN74ALS109ANSRG4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74ALS109ANSRG4 | SN74ALS109ANSRG4 |
SN74ALS109A 应用技术支持与电子电路设计开发资源下载
- SN74ALS109A 数据资料 dataSheet 下载.PDF
- TI 德州仪器触发器/锁存器/寄存器产品选型与价格 . xls
- Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
- Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
- TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
- Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
- CMOS Power Consumption and CPD Calculation (PDF 89 KB)
- Designing With Logic (PDF 186 KB)
- Live Insertion (PDF 150 KB)
- Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
- Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- LOGIC Pocket Data Book (PDF 6001 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- Logic Cross-Reference (PDF 2938 KB)
