SN74AUC02 四路 2 输入正或非门

This quadruple 2-input positive-NOR gate is operational at 0.8-V to 2.7-V VCC, but is designed specifically for 1.65-V to 1.95-V VCC operation.

The SN74AUC02 device performs the Boolean function Y = (A + B)\ or Y = A\ × B\ in positive logic.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down

SN74AUC02
Rating Catalog 
Technology Family AUC  
SN74AUC02 特性
SN74AUC02 芯片订购指南
器件 状态 温度 价格 封装 | 引脚 封装数量 | 封装载体 丝印标记
SN74AUC02RGYR ACTIVE -40 to 85 0.48 | 1ku VQFN (RGY) | 14 3000 | LARGE T&R  
SN74AUC02RGYRG4 ACTIVE -40 to 85 0.48 | 1ku VQFN (RGY) | 14 3000 | LARGE T&R  
SN74AUC02 质量与无铅数据
器件 环保计划* 铅/焊球涂层 MSL 等级/回流焊峰 环保信息与无铅 (Pb-free) DPPM / MTBF / FIT 率
SN74AUC02RGYR Green (RoHS & no Sb/Br)  CU NIPDAU  Level-2-260C-1 YEAR SN74AUC02RGYR SN74AUC02RGYR
SN74AUC02RGYRG4 Green (RoHS & no Sb/Br)  CU NIPDAU  Level-2-260C-1 YEAR SN74AUC02RGYRG4 SN74AUC02RGYRG4
SN74AUC02 应用技术支持与电子电路设计开发资源下载
  1. SN74AUC02 数据资料 dataSheet 下载.PDF
  2. TI 德州仪器门电路产品选型与价格 . xls
  3. Logic Guide 2009 (PDF 4263 KB)
  4. Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
  5. Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
  6. TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
  7. Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
  8. CMOS Power Consumption and CPD Calculation (PDF 89 KB)
  9. Designing With Logic (PDF 186 KB)
  10. Live Insertion (PDF 150 KB)
  11. Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
  12. Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
  13. HiRel Unitrode Power Management Brochure (PDF 206 KB)
  14. LOGIC Pocket Data Book (PDF 6001 KB)
  15. HiRel Unitrode Power Management Brochure (PDF 206 KB)
  16. Logic Cross-Reference (PDF 2938 KB)