SN74AUCH32374 具有三态输出的 32 位边沿 D 类触发器
This 32-bit edge-triggered D-type flip-flop is operational at 0.8-V to 2.7-V VCC, but is designed specifically for 1.65-V to 1.95-V VCC operation.
The SN74AUCH32374 is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. It can be used as four 8-bit flip-flops, two 16-bit flip-flops, or one 32-bit flip-flop. On the positive transition of the clock (CLK) input, the Q outputs of the flip-flop take on the logic levels set up at the data (D) inputs.
A buffered output-enable (OE)\ input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly
|
SN74AUCH32374 |
| Vcc range(V) |
0.8 to 2.7 |
| Output Drive(mA) |
-9/9 |
| No. of Bits |
32 |
| Static Current |
0.04 |
| th(ns) |
0.4 |
| tpd max(ns) |
2.2 |
| tsu(ns) |
0.6 |
| Logic |
True |
| Technology Family |
AUC |
| Rating |
Catalog |
SN74AUCH32374 特性
- Member of the Texas Instruments Widebus+™ Family
- Optimized for 1.8-V Operation and is 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation
- Ioff Supports Partial-Power-Down Mode Operation
- Sub 1-V Operable
- Max tpd of 2.8 ns at 1.8 V
- Low Power Consumption, 40-µA Max ICC
- ±8-mA Output Drive at 1.8 V
- Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
- Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
- ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)
SN74AUCH32374 芯片订购指南
| 器件 |
状态 |
温度 |
价格（美元） |
封装 | 引脚 |
封装数量 | 封装载体 |
丝印标记 |
| SN74AUCH32374GKER |
NRND |
-40 to 85 |
5.90 | 1ku |
LFBGA (GKE) | 96 |
1000 | LARGE T&R |
MK374 |
| SN74AUCH32374ZKER |
ACTIVE |
-40 to 85 |
2.80 | 1ku |
LFBGA (ZKE) | 96 |
1000 | LARGE T&R |
MK374 |
SN74AUCH32374 质量与无铅数据
| 器件 |
环保计划* |
铅/焊球涂层 |
MSL 等级/回流焊峰 |
环保信息与无铅 (Pb-free) |
DPPM / MTBF / FIT 率 |
| SN74AUCH32374GKER |
TBD |
SNPB |
Level-2-235C-1 YEAR |
SN74AUCH32374GKER |
SN74AUCH32374GKER |
| SN74AUCH32374ZKER |
Green (RoHS & no Sb/Br) |
SNAGCU |
Level-3-260C-168 HR |
SN74AUCH32374ZKER |
SN74AUCH32374ZKER |
SN74AUCH32374 应用技术支持与电子电路设计开发资源下载
- SN74AUCH32374 数据资料 dataSheet 下载.PDF
- TI 德州仪器触发器/锁存器/寄存器产品选型与价格 . xls
- Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
- Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
- TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
- Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
- CMOS Power Consumption and CPD Calculation (PDF 89 KB)
- Designing With Logic (PDF 186 KB)
- Live Insertion (PDF 150 KB)
- Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
- Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- LOGIC Pocket Data Book (PDF 6001 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- Logic Cross-Reference (PDF 2938 KB)
