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SN74AUP2G125 具有三态输出的低功耗双路总线缓冲器闸

The AUP family is TI’s premier solution to the industry’s low-power needs in battery-powered portable applications. This family ensures a very low static and dynamic power consumption across the entire VCC range of 0.8 V to 3.6 V, resulting in an increased battery life. This product also maintains excellent signal integrity (see Figure 1 and Figure 2).

The SN74AUP2G125 is a dual bus buffer gate designed for 0.8-V to 3.6-V VCC operation. This device features dual line drivers with 3-state outputs. Each output is disabled when the corresponding output-enable (OE) input is high. This device has the input-disable feature, which allows floating input signals.

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver

	SN74AUP2G125
Pin/Package	8DSBGA, 8UQFN, 8US8, 8X2SON
Operating Temperature Range(°C)	-40 to 85
Technology Family	AUP
Approx. Price (US$)	0.23 | 1ku
Rating	Catalog

SN74AUP2G125 特性

• Available in the Texas Instruments NanoStar™ Package
• Low Static-Power Consumption (ICC = 0.9 µA Max)
• Low Dynamic-Power Consumption (Cpd = 4 pF Typ at 3.3 V)
• Low Input Capacitance (CI = 1.5 pF Typ)
• Low Noise – Overshoot and Undershoot <10% of VCC
• Input-Disable Feature Allows Floating Input Conditions
• Ioff Supports Partial-Power-Down Mode Operation
• Input Hysteresis Allows Slow Input Transition and Better Switching Noise Immunity at Input
• Wide Operating VCC Range of 0.8 V to 3.6 V
• Optimized for 3.3-V Operation
• 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation
• tpd = 5.4 ns Max at 3.3 V
• Suitable for Point-to-Point Applications
• Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
• ESD Performance Tested Per JESD 22
  • 2000-V Human-Body Model (A114-B, Class II)
  • 1000-V Charged-Device Model (C101)

SN74AUP2G125 芯片订购指南

器件	状态	温度	价格	封装 | 引脚	封装数量 | 封装载体	丝印标记
SN74AUP2G125DCUR	ACTIVE	-40 to 85	0.24 | 1ku	US8 (DCU) | 8	3000 | LARGE T&R
SN74AUP2G125DQER	ACTIVE	-40 to 85	0.23 | 1ku	X2SON (DQE) | 8	5000 | LARGE T&R
SN74AUP2G125RSER	ACTIVE	-40 to 85	0.24 | 1ku	UQFN (RSE) | 8	5000 | LARGE T&R
SN74AUP2G125YFPR	ACTIVE	-40 to 85	0.33 | 1ku	DSBGA (YFP) | 8	3000 | LARGE T&R
SN74AUP2G125YZPR	ACTIVE	-40 to 85	0.35 | 1ku	DSBGA (YZP) | 8	3000 | LARGE T&R

SN74AUP2G125 质量与无铅数据

器件	环保计划*	铅/焊球涂层	MSL 等级/回流焊峰	环保信息与无铅 (Pb-free)	DPPM / MTBF / FIT 率
SN74AUP2G125DCUR	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-1-260C-UNLIM	SN74AUP2G125DCUR	SN74AUP2G125DCUR
SN74AUP2G125DQER	Green (RoHS & no Sb/Br)	NIPDAU	Level-1-260C-UNLIM	SN74AUP2G125DQER	SN74AUP2G125DQER
SN74AUP2G125RSER	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-1-260C-UNLIM	SN74AUP2G125RSER	SN74AUP2G125RSER
SN74AUP2G125YFPR	Green (RoHS & no Sb/Br)	SNAGCU	Level-1-260C-UNLIM	SN74AUP2G125YFPR	SN74AUP2G125YFPR
SN74AUP2G125YZPR	Green (RoHS & no Sb/Br)	SNAGCU	Level-1-260C-UNLIM	SN74AUP2G125YZPR	SN74AUP2G125YZPR

SN74AUP2G125 应用技术支持与电子电路设计开发资源下载

1. SN74AUP2G125 数据资料 dataSheet 下载.PDF
2. TI 德州仪器小尺寸逻辑器件产品选型与价格 . xls
3. Logic Guide 2009 (PDF 4263 KB)
4. Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
5. Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
6. TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
7. Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
8. CMOS Power Consumption and CPD Calculation (PDF 89 KB)
9. Designing With Logic (PDF 186 KB)
10. Live Insertion (PDF 150 KB)
11. Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
12. Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
13. HiRel Unitrode Power Management Brochure (PDF 206 KB)
14. LOGIC Pocket Data Book (PDF 6001 KB)
15. HiRel Unitrode Power Management Brochure (PDF 206 KB)
16. Logic Cross-Reference (PDF 2938 KB)