SN74AVC4T774 具有可配置电压转换和 3 态输出的 4 位双电源总线收发器
This 4-bit noninverting bus transceiver uses two separate configurable power-supply rails. The A port is designed to track VCCA. VCCA accepts any supply voltage from 1.2 V to 3.6 V. The B port is designed to track VCCB. VCCB accepts any supply voltage from 1.2 V to 3.6 V. The SN74AVC4T774 is optimized to operate with VCCA/VCCB set at 1.4 V to 3.6 V. It is operational with VCCA/VCCB as low as 1.2 V. This allows for universal low-voltage bidirectional translation between any of the 1.2-V, 1.5-V, 1.8-V, 2.5-V, and 3.3-V voltage nodes.
The SN74AVC4T774 is designed for asynchronous communication between data buses. The logic levels of the direction-control (DIR) input and the output-enable (OE) input activate either the B-port outputs or the A-port outputs or place both output ports in the high-impedance mode. The device transmits data from the A bus to the B bus when the B outputs are activated, and from the B bus to the A bus when the A outputs are activated. The input circuitry on both A and B ports is always active and must have a logic HIGH or LOW level applied to prevent excess ICC and ICCZ.
The SN74AVC4T774 is designed so that the control pins (DIR1, DIR2, DIR3, DIR4, and OE) are supplied by VCCA.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
The VCC isolation feature ensures that if either VCC input is at GND, then both ports are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to VCCA through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Since this device has CMOS inputs, it is very important to not allow them to float. If the inputs are not driven to either a high VCC state, or a low GND state, an undesirable larger than expected ICC current may result. Since the input voltage settlement is governed by many factors (e.g. capacitance, board-layout, package inductance, surrounding conditions, etc.), ensuring that they these inputs are kept out of erroneous switching states and tying them to either a high or a low level minimizes the leakage-current
| SN74AVC4T774 | |
| Vcc range(V) | 1.2 to 3.6 |
| No. of Bits | 4 |
| No. of Outputs | 2 |
| Bus Drive(ma) | -12,12 |
| Output Drive(mA) | -12,12 |
| Technology Family | AVC |
| Vmin(V) | 1.2 |
| Vmax(V) | 3.6 |
| Pin/Package | 16TSSOP, 16VQFN, 16UQFN |
| Operating Temperature Range(°C) | -40 to 85 |
| Approx. Price (US$) | 0.70 | 1ku |
| Rating | Catalog |
SN74AVC4T774 特性
- Each Channel Has an Independent DIR Control Input
- Control Inputs VIH/VIL Levels Are Referenced to VCCA Voltage
- Fully Configurable Dual-Rail Design Allows Each Port to Operate Over the Full 1.2-V to 3.6-V Power-Supply Range
- I/Os Are 4.6-V Tolerant
- Ioff Supports Partial Power-Down-Mode Operation
- Typical Data Rates
- 380 Mbps (1.8-V to 3.3-V Translation)
- 200 Mbps (<1.8-V to 3.3-V Translation)
- 200 Mbps (Translate to 2.5 V or 1.8 V)
- 150 Mbps (Translate to 1.5 V)
- 100 Mbps (Translate to 1.2 V)
- Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
- ESD Protection Exceeds the Following Levels (tested per JESD 22)
- 8000-V Human-Body Model (A114-A)
- 250-V Machine Model (A115-A)
- 1500-V Charged-Device Model (C101)
SN74AVC4T774 芯片订购指南
| 器件 | 状态 | 温度 | 价格（美元） | 封装 | 引脚 | 封装数量 | 封装载体 | 丝印标记 |
| 74AVC4T774RGYRG4 | ACTIVE | -40 to 85 | 0.80 | 1ku | VQFN (RGY) | 16 | 3000 | LARGE T&R | |
| 74AVC4T774RSVRG4 | ACTIVE | -40 to 85 | 0.80 | 1ku | UQFN (RSV) | 16 | 3000 | LARGE T&R | |
| SN74AVC4T774PW | ACTIVE | -40 to 85 | 0.85 | 1ku | TSSOP (PW) | 16 | 90 | TUBE | |
| SN74AVC4T774PWG4 | ACTIVE | -40 to 85 | 0.85 | 1ku | TSSOP (PW) | 16 | 90 | TUBE | |
| SN74AVC4T774PWR | ACTIVE | -40 to 85 | 0.70 | 1ku | TSSOP (PW) | 16 | 2000 | LARGE T&R | |
| SN74AVC4T774PWRG4 | ACTIVE | -40 to 85 | 0.70 | 1ku | TSSOP (PW) | 16 | 2000 | LARGE T&R | |
| SN74AVC4T774RGYR | ACTIVE | -40 to 85 | 0.80 | 1ku | VQFN (RGY) | 16 | 3000 | LARGE T&R | |
| SN74AVC4T774RSVR | ACTIVE | -40 to 85 | 0.80 | 1ku | UQFN (RSV) | 16 | 3000 | LARGE T&R |
SN74AVC4T774 质量与无铅数据
| 器件 | 环保计划* | 铅/焊球涂层 | MSL 等级/回流焊峰 | 环保信息与无铅 (Pb-free) | DPPM / MTBF / FIT 率 |
| 74AVC4T774RGYRG4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-2-260C-1 YEAR | 74AVC4T774RGYRG4 | 74AVC4T774RGYRG4 |
| 74AVC4T774RSVRG4 | TBD | Call TI | Call TI | 74AVC4T774RSVRG4 | 74AVC4T774RSVRG4 |
| SN74AVC4T774PW | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74AVC4T774PW | SN74AVC4T774PW |
| SN74AVC4T774PWG4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74AVC4T774PWG4 | SN74AVC4T774PWG4 |
| SN74AVC4T774PWR | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74AVC4T774PWR | SN74AVC4T774PWR |
| SN74AVC4T774PWRG4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74AVC4T774PWRG4 | SN74AVC4T774PWRG4 |
| SN74AVC4T774RGYR | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-2-260C-1 YEAR | SN74AVC4T774RGYR | SN74AVC4T774RGYR |
| SN74AVC4T774RSVR | TBD | Call TI | Call TI | SN74AVC4T774RSVR | SN74AVC4T774RSVR |
SN74AVC4T774 应用技术支持与电子电路设计开发资源下载
- SN74AVC4T774 数据资料 dataSheet 下载.PDF
- TI 德州仪器电压电平转换产品选型与价格 . xls
- Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
- Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
- TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
- Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
- CMOS Power Consumption and CPD Calculation (PDF 89 KB)
- Designing With Logic (PDF 186 KB)
- Live Insertion (PDF 150 KB)
- Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
- Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- LOGIC Pocket Data Book (PDF 6001 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- Logic Cross-Reference (PDF 2938 KB)
