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SN74F112 具有清零和预设功能的双路 J-K 下降沿触发器

The SN74F112 contains two independent J-K negative-edge-triggered flip-flops. A low level at the preset () or clear () inputs sets or resets the outputs regardless of the levels of the other inputs. When and are inactive (high), data at the J and K inputs meeting the setup time requirements is transferred to the outputs on the negative-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the J and K inputs may be changed without affecting the levels at the outputs. The SN74F112 can perform as a toggle flip-flop by tying J and K high.

The SN74F112 is characterized for operation from 0°C to 70°C

	SN74F112
Voltage Nodes(V)	5
Technology Family	ALS
Rating	Catalog

SN74F112 特性

• Package Options Include Plastic Small-Outline Packages and Standard Plastic 300-mil DIPs

SN74F112 芯片订购指南

器件	状态	温度	价格	封装 | 引脚	封装数量 | 封装载体	丝印标记
SN74F112D	ACTIVE	0 to 70	0.90 | 1ku	SOIC (D) | 16	40 | TUBE	F112
SN74F112DE4	ACTIVE	0 to 70	0.90 | 1ku	SOIC (D) | 16	40 | TUBE	F112
SN74F112DG4	ACTIVE	0 to 70	0.90 | 1ku	SOIC (D) | 16	40 | TUBE	F112
SN74F112DR	ACTIVE	0 to 70	0.75 | 1ku	SOIC (D) | 16	2500 | LARGE T&R	F112
SN74F112DRE4	ACTIVE	0 to 70	0.75 | 1ku	SOIC (D) | 16	2500 | LARGE T&R	F112
SN74F112DRG4	ACTIVE	0 to 70	0.75 | 1ku	SOIC (D) | 16	2500 | LARGE T&R	F112
SN74F112N	ACTIVE	0 to 70	0.85 | 1ku	PDIP (N) | 16	25 | TUBE	SN74F112N
SN74F112N3	OBSOLETE	0 to 70		PDIP (N) | 16
SN74F112NE4	ACTIVE	0 to 70	0.85 | 1ku	PDIP (N) | 16	25 | TUBE	SN74F112N
SN74F112NSR	ACTIVE	0 to 70	0.85 | 1ku	SO (NS) | 16	2000 | LARGE T&R	F112
SN74F112NSRE4	ACTIVE	0 to 70	0.85 | 1ku	SO (NS) | 16	2000 | LARGE T&R	F112
SN74F112NSRG4	ACTIVE	0 to 70	0.85 | 1ku	SO (NS) | 16	2000 | LARGE T&R	F112

SN74F112 质量与无铅数据

器件	环保计划*	铅/焊球涂层	MSL 等级/回流焊峰	环保信息与无铅 (Pb-free)	DPPM / MTBF / FIT 率
SN74F112D	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-1-260C-UNLIM	SN74F112D	SN74F112D
SN74F112DE4	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-1-260C-UNLIM	SN74F112DE4	SN74F112DE4
SN74F112DG4	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-1-260C-UNLIM	SN74F112DG4	SN74F112DG4
SN74F112DR	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-1-260C-UNLIM	SN74F112DR	SN74F112DR
SN74F112DRE4	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-1-260C-UNLIM	SN74F112DRE4	SN74F112DRE4
SN74F112DRG4	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-1-260C-UNLIM	SN74F112DRG4	SN74F112DRG4
SN74F112N	Pb-Free (RoHS)	CU NIPDAU	N/A for Pkg Type	SN74F112N	SN74F112N
SN74F112NE4	Pb-Free (RoHS)	CU NIPDAU	N/A for Pkg Type	SN74F112NE4	SN74F112NE4
SN74F112NSR	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-1-260C-UNLIM	SN74F112NSR	SN74F112NSR
SN74F112NSRE4	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-1-260C-UNLIM	SN74F112NSRE4	SN74F112NSRE4
SN74F112NSRG4	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-1-260C-UNLIM	SN74F112NSRG4	SN74F112NSRG4

SN74F112 应用技术支持与电子电路设计开发资源下载

1. SN74F112 数据资料 dataSheet 下载.PDF
2. TI 德州仪器触发器/锁存器/寄存器产品选型与价格 . xls
3. Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
4. Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
5. TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
6. Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
7. CMOS Power Consumption and CPD Calculation (PDF 89 KB)
8. Designing With Logic (PDF 186 KB)
9. Live Insertion (PDF 150 KB)
10. Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
11. Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
12. HiRel Unitrode Power Management Brochure (PDF 206 KB)
13. LOGIC Pocket Data Book (PDF 6001 KB)
14. HiRel Unitrode Power Management Brochure (PDF 206 KB)
15. Logic Cross-Reference (PDF 2938 KB)