SN74F574 具有三态输出的八路 D 类边沿触发器
This 8-bit flip-flop features 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. It is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.
The eight flip-flops of the SN74F574 are edge-triggered D-type flip-flops. On the positive transition of the clock (CLK) input, the Q outputs will be set to the logic levels that were set up at the data (D) inputs.
A buffered output enable 
input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly
| SN74F574 | |
| Voltage Nodes(V) | 5 |
| Vcc range(V) | 4.5 to 5.5 |
| Input Level | TTL |
| Output Level | TTL |
| Output Drive(mA) | -3/24 |
| No. of Outputs | 8 |
| th(ns) | 2 |
| tpd max(ns) | 10 |
| tsu(ns) | 2 |
| Logic | True |
| Technology Family | F |
| Rating | Catalog |
SN74F574 特性
- Eight D-Type Flip-Flops in a Single Package
- 3-State Bus-Driving True Outputs
- Full Parallel Access for Loading
- Buffered Control Inputs
- Package Options Include Plastic Small-Outline Packages and Standard Plastic 300-mil DIPs
SN74F574 芯片订购指南
| 器件 | 状态 | 温度 | 价格（美元） | 封装 | 引脚 | 封装数量 | 封装载体 | 丝印标记 |
| SN74F574DW | ACTIVE | 0 to 70 | 1.10 | 1ku | SOIC (DW) | 20 | 25 | TUBE | F574 |
| SN74F574DWE4 | ACTIVE | 0 to 70 | 1.10 | 1ku | SOIC (DW) | 20 | 25 | TUBE | F574 |
| SN74F574DWG4 | ACTIVE | 0 to 70 | 0.90 | 1ku | SOIC (DW) | 20 | 2000 | LARGE T&R | F574 |
| SN74F574DWR | ACTIVE | 0 to 70 | 0.90 | 1ku | SOIC (DW) | 20 | 2000 | LARGE T&R | F574 |
| SN74F574DWRE4 | ACTIVE | 0 to 70 | 0.90 | 1ku | SOIC (DW) | 20 | 2000 | LARGE T&R | F574 |
| SN74F574DWRG4 | ACTIVE | 0 to 70 | 0.90 | 1ku | SOIC (DW) | 20 | 2000 | LARGE T&R | F574 |
| SN74F574N | ACTIVE | 0 to 70 | 1.00 | 1ku | PDIP (N) | 20 | 20 | TUBE | SN74F574N |
| SN74F574N3 | OBSOLETE | 0 to 70 | PDIP (N) | 20 | SN74F574N | ||
| SN74F574NE4 | ACTIVE | 0 to 70 | 1.00 | 1ku | PDIP (N) | 20 | 20 | TUBE | SN74F574N |
| SN74F574NSR | ACTIVE | 0 to 70 | 1.00 | 1ku | SO (NS) | 20 | 2000 | LARGE T&R | F574 |
| SN74F574NSRE4 | ACTIVE | 0 to 70 | 1.00 | 1ku | SO (NS) | 20 | 2000 | LARGE T&R | F574 |
| SN74F574NSRG4 | ACTIVE | 0 to 70 | 1.00 | 1ku | SO (NS) | 20 | 2000 | LARGE T&R | F574 |
SN74F574 质量与无铅数据
| 器件 | 环保计划* | 铅/焊球涂层 | MSL 等级/回流焊峰 | 环保信息与无铅 (Pb-free) | DPPM / MTBF / FIT 率 |
| SN74F574DW | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74F574DW | SN74F574DW |
| SN74F574DWE4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74F574DWE4 | SN74F574DWE4 |
| SN74F574DWG4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74F574DWG4 | SN74F574DWG4 |
| SN74F574DWR | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74F574DWR | SN74F574DWR |
| SN74F574DWRE4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74F574DWRE4 | SN74F574DWRE4 |
| SN74F574DWRG4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74F574DWRG4 | SN74F574DWRG4 |
| SN74F574N | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74F574N | SN74F574N |
| SN74F574N3 | Pb-Free (RoHS) | CU NIPDAU | N/A for Pkg Type | SN74F574N3 | SN74F574N3 |
| SN74F574NE4 | Pb-Free (RoHS) | CU NIPDAU | N/A for Pkg Type | SN74F574NE4 | SN74F574NE4 |
| SN74F574NSR | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74F574NSR | SN74F574NSR |
| SN74F574NSRE4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74F574NSRE4 | SN74F574NSRE4 |
| SN74F574NSRG4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74F574NSRG4 | SN74F574NSRG4 |
SN74F574 应用技术支持与电子电路设计开发资源下载
- SN74F574 数据资料 dataSheet 下载.PDF
- TI 德州仪器触发器/锁存器/寄存器产品选型与价格 . xls
- Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
- Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
- TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
- Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
- CMOS Power Consumption and CPD Calculation (PDF 89 KB)
- Designing With Logic (PDF 186 KB)
- Live Insertion (PDF 150 KB)
- Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
- Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- LOGIC Pocket Data Book (PDF 6001 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- Logic Cross-Reference (PDF 2938 KB)
