SN74GTLP21395 具有独立 LVTTL 端口、Fdbk 路径和可选择极性的双路 1 位 LVTTL/GTLP 可调节边沿速率总线 Xcvrs
The SN74GTLP21395 is two 1-bit, high-drive, 3-wire bus transceivers that provide LVTTL-to-GTLP and GTLP-to-LVTTL signal-level translation for applications, such as primary and secondary clocks, that require individual output-enable and true/complement controls. The device allows for transparent and inverted transparent modes of data transfer with separate LVTTL input and LVTTL output pins, which provide a feedback path for control and diagnostics monitoring. The device provides a high-speed interface between cards operating at LVTTL logic levels and a backplane operating at GTLP signal levels and is designed especially to work with the Texas Instruments 3.3-V 1394 backplane physical-layer controller. High-speed (about three times faster than standard LVTTL or TTL) backplane operation is a direct result of GTLP reduced output swing (<1 V), reduced input threshold levels, improved differential input, OEC™ circuitry, and TI-OPC™ circuitry.
|
SN74GTLP21395 |
| Voltage Nodes(V) |
3.3 |
| A Side |
LVTTL |
| B Side |
GTL |
| No. of Bits |
2 |
| Static Current |
20 mA |
| Rating |
Catalog |
| Technology Family |
GTLP |
SN74GTLP21395 特性
- TI-OPC™ Circuitry Limits Ringing on Unevenly Loaded Backplanes
- OEC™ Circuitry Improves Signal Integrity and Reduces Electromagnetic Interference
- Bidirectional Interface Between GTLP Signal Levels and LVTTL Logic Levels
- Split LVTTL Port Provides a Feedback Path for Control and Diagnostics Monitoring
- Y Outputs Have Equivalent 26- Series Resistors, So No External Resistors Are Required
- LVTTL Interfaces Are 5-V Tolerant
- High-Drive GTLP Outputs (100 mA)
- LVTTL Outputs (–12 mA/12 mA)
- Variable Edge-Rate Control (ERC) Input Selects GTLP Rise and Fall Times for Optimal Data-Transfer Rate and Signal Integrity in Distributed Loads
- Ioff, Power-Up 3-State, and BIAS VCC Support Live Insertion
- Polarity Control Selects True or Complementary Outputs
- Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
- ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)
SN74GTLP21395 芯片订购指南
| 器件 |
状态 |
温度 |
价格（美元） |
封装 | 引脚 |
封装数量 | 封装载体 |
丝印标记 |
| SN74GTLP21395DW |
ACTIVE |
-40 to 85 |
3.05 | 1ku |
SOIC (DW) | 20 |
25 | TUBE |
|
| SN74GTLP21395DWE4 |
ACTIVE |
-40 to 85 |
3.05 | 1ku |
SOIC (DW) | 20 |
25 | TUBE |
|
| SN74GTLP21395DWG4 |
ACTIVE |
-40 to 85 |
3.05 | 1ku |
SOIC (DW) | 20 |
25 | TUBE |
|
SN74GTLP21395 质量与无铅数据
| 器件 |
环保计划* |
铅/焊球涂层 |
MSL 等级/回流焊峰 |
环保信息与无铅 (Pb-free) |
DPPM / MTBF / FIT 率 |
| SN74GTLP21395DW |
Green (RoHS & no Sb/Br) |
CU NIPDAU |
Level-1-260C-UNLIM |
SN74GTLP21395DW |
SN74GTLP21395DW |
| SN74GTLP21395DWE4 |
Green (RoHS & no Sb/Br) |
CU NIPDAU |
Level-1-260C-UNLIM |
SN74GTLP21395DWE4 |
SN74GTLP21395DWE4 |
| SN74GTLP21395DWG4 |
Green (RoHS & no Sb/Br) |
CU NIPDAU |
Level-1-260C-UNLIM |
SN74GTLP21395DWG4 |
SN74GTLP21395DWG4 |
SN74GTLP21395 应用技术支持与电子电路设计开发资源下载
- SN74GTLP21395 数据资料 dataSheet 下载.PDF
- TI 德州仪器缓冲器、驱动器/收发器产品选型与价格 . xls
- CMOS 非缓冲反向器在振荡器电路中的使用 (PDF 951 KB)
- Semiconductor Packing Methodology (PDF 3005 KB)
- 逻辑产品选择指南 2006/2007 （修订版 Z）(4462KB)
- 标准线性和逻辑产品 5 分钟指南 (786KB)
- 了解和解释标准逻辑数据表
- LOGIC Pocket Data Book (PDF 6001 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- Logic Cross-Reference (PDF 2938 KB)
