SN74GTLPH1627 具有源异步时钟输出的 18 位 LVTTL 到 GTLP 总线 Xcvr

SN74GTLPH1627 描述

The SN74GTLPH1627 is a high-drive, 18-bit bus transceiver that provides LVTTL-to-GTLP and GTLP-to-LVTTL signal-level translation. The device allows for transparent and latched modes of data transfer. Additionally, with the use of the clock-mode select (CMS) input, the device can be used in source synchronous and clock synchronous applications. Source synchronous applications require the skew between the clock output and data output to be minimized for optimum maximum-frequency system performance. In order to reduce this skew, aflexible setup time adjustment (FSTA) feature is incorporated into the device that sets a predetermined delay between the clock and data. The CMS and direction (DIR) inputs control the mode of the device.

SN74GTLPH1627
Voltage Nodes(V) 3.3  
A Side LVTTL/TTL/5-V CMOS  
B Side GTLP  
Bus Drive(ma) -24/24  
No. of Bits 18  
Static Current 50 mA  
Rating Catalog  
Technology Family GTLP
SN74GTLPH1627 特性
SN74GTLPH1627 芯片订购指南
器件 状态 温度 价格(美元) 封装 | 引脚 封装数量 | 封装载体 丝印标记
SN74GTLPH1627DGGR ACTIVE -40 to 85 14.40 | 1ku TSSOP (DGG) | 64 2000 | LARGE T&R  
SN74GTLPH1627 质量与无铅数据
器件 环保计划* 铅/焊球涂层 MSL 等级/回流焊峰 环保信息与无铅 (Pb-free) DPPM / MTBF / FIT 率
SN74GTLPH1627RCR Green (RoHS & no Sb/Br)  CU NIPDAU  Level-1-260C-UNLIM SN74GTLPH1627RCR SN74GTLPH1627RCR
SN74GTLPH1627 应用技术支持与电子电路设计开发资源下载
  1. SN74GTLPH1627 数据资料 dataSheet 下载.PDF
  2. TI 德州仪器缓冲器、驱动器/收发器产品选型与价格 . xls
  3. CMOS 非缓冲反向器在振荡器电路中的使用 (PDF 951 KB)
  4. Semiconductor Packing Methodology (PDF 3005 KB)
  5. 逻辑产品选择指南 2006/2007 (修订版 Z)(4462KB)
  6. 标准线性和逻辑产品 5 分钟指南 (786KB)
  7. 了解和解释标准逻辑数据表
  8. LOGIC Pocket Data Book (PDF 6001 KB)
  9. HiRel Unitrode Power Management Brochure (PDF 206 KB)
  10. Logic Cross-Reference (PDF 2938 KB)