SN74HSTL162822 14 位至 28 位 HSTL 至 LVTTL 内存地址锁存器
This 14-bit to 28-bit D-type latch is designed for 3.15-V to 3.45-V VCC operation. HSTL levels are expected on the inputs. LVTTL levels are driven on the Q outputs.
All outputs are designed to sink up to 12 mA and include 25- 
series resistors to reduce overshoot and undershoot.
The SN74HSTL162822 is particularly suitable for driving an address bus to two banks of memory. Each bank of 14 outputs is controlled with its own latch-enable (
) input.
Each of the 14 data (D) inputs is tied to the inputs of two D-type latches, which provide true data at the outputs. While LE\ is low, the outputs (Q) of the corresponding 14 latches follow the D inputs. When is taken high, the Q outputs are latched at the levels set up at the D inputs
| SN74HSTL162822 | |
| Voltage Nodes(V) | 3.3 |
| Input Level | HSTL |
| Output Level | LVTTL |
| Technology Family | HSTL |
| Rating | Catalog |
SN74HSTL162822 特性
- Member of the Texas Instruments WidebusTM Family
- Inputs Meet JEDEC HSTL Standard JESD8-6
- All Outputs Have Equivalent 25- Series Resistors
- Packaged in Plastic Thin Shrink Small-Outline Package
SN74HSTL162822 芯片订购指南
| 器件 | 状态 | 温度 | 价格（美元） | 封装 | 引脚 | 封装数量 | 封装载体 | 丝印标记 |
| 74HSTL162822DGGRE4 | ACTIVE | -40 to 85 | 8.80 | 1ku | TSSOP (DGG) | 64 | 2000 | LARGE T&R | |
| 74HSTL162822DGGRG4 | ACTIVE | -40 to 85 | 8.80 | 1ku | TSSOP (DGG) | 64 | 2000 | LARGE T&R | |
| SN74HSTL162822DGGR | ACTIVE | -40 to 85 | 8.80 | 1ku | TSSOP (DGG) | 64 | 2000 | LARGE T&R |
SN74HSTL162822 质量与无铅数据
| 器件 | 环保计划* | 铅/焊球涂层 | MSL 等级/回流焊峰 | 环保信息与无铅 (Pb-free) | DPPM / MTBF / FIT 率 |
| 74HSTL162822DGGRE4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | 74HSTL162822DGGRE4 | 74HSTL162822DGGRE4 |
| 74HSTL162822DGGRG4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | 74HSTL162822DGGRG4 | 74HSTL162822DGGRG4 |
| SN74HSTL162822DGGR | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74HSTL162822DGGR | SN74HSTL162822DGGR |
SN74HSTL162822 应用技术支持与电子电路设计开发资源下载
- SN74HSTL162822 数据资料 dataSheet 下载.PDF
- TI 德州仪器特殊逻辑产品选型与价格 . xls
- Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
- Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
- TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
- Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
- CMOS Power Consumption and CPD Calculation (PDF 89 KB)
- Designing With Logic (PDF 186 KB)
- Live Insertion (PDF 150 KB)
- Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
- Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- LOGIC Pocket Data Book (PDF 6001 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- Logic Cross-Reference (PDF 2938 KB)
