The 'LS673 is a 16-bit shift register and a 16-bit storage register in a single 24-pin package. A three-state input/output (SER/Q15) port to the shift register allows serial entry and/or reading of data. The storage register is connected in a parallel data loop with the shift register and may be asynchronously cleared by taking the store-clear input low. The storage register may be parallel loaded with shift-register data to provide shift-register status via the parallel outputs. The shift register can be parallel loaded with the storage-register data upon commmand.
A high logic level at the chip-level (CS\) input disables both the shift-register clock and the storage register clock and places SER/Q15 in the high-impedance state
SN74LS674 | |
Technology Family | ALS |
Rating | Catalog |
器件 | 状态 | 温度 | 价格 | 封装 | 引脚 | 封装数量 | 封装载体 | 丝印标记 |
SN74LS674DW | ACTIVE | 0 to 70 | 49.90 | 1ku | SOIC(DW) | 24 | 25 | TUBE | |
SN74LS674DWE4 | ACTIVE | 0 to 70 | 49.90 | 1ku | SOIC(DW) | 24 | 25 | TUBE | |
SN74LS674DWG4 | ACTIVE | 0 to 70 | 49.90 | 1ku | SOIC(DW) | 24 | 25 | TUBE | |
SN74LS674N | ACTIVE | 0 to 70 | 54.90 | 1ku | PDIP (N) | 24 | 15 | TUBE | |
SN74LS674NE4 | ACTIVE | 0 to 70 | 54.90 | 1ku | PDIP (N) | 24 | 15 | TUBE |
器件 | 环保计划* | 铅/焊球涂层 | MSL 等级/回流焊峰 | 环保信息与无铅 (Pb-free) | DPPM / MTBF / FIT 率 |
SN74LS674DW | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74LS674DW | SN74LS674DW |
SN74LS674DWE4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74LS674DWE4 | SN74LS674DWE4 |
SN74LS674DWG4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74LS674DWG4 | SN74LS674DWG4 |
SN74LS674N | Pb-Free (RoHS) | CU NIPDAU | N/A for Pkg Type | SN74LS674N | SN74LS674N |
SN74LS674NE4 | Pb-Free (RoHS) | CU NIPDAU | N/A for Pkg Type | SN74LS674NE4 | SN74LS674NE4 |