SN74LV11A-Q1 汽车类三路 3 输入正与门

This triple 3-input positive-AND gate is designed for 2-V to 5.5-V VCC operation.

The SN74LV11A performs the Boolean function Y = A • B • C or Y = (A\ + B\ + C\) in positive logic

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down

SN74LV11A-Q1
Rating Automotive
Technology Family LV-A  
SN74LV11A-Q1 特性
SN74LV11A-Q1 芯片订购指南
器件 状态 温度 价格 封装 | 引脚 封装数量 | 封装载体 丝印标记
SN74LV11ATPWRG4Q1 ACTIVE -40 to 105 0.39 | 1ku TSSOP (PW) | 14 2000  
SN74LV11ATPWRQ1 ACTIVE -40 to 105 0.39 | 1ku TSSOP (PW) | 14 2000  
SN74LV11A-Q1 质量与无铅数据
器件 环保计划* 铅/焊球涂层 MSL 等级/回流焊峰 环保信息与无铅 (Pb-free) DPPM / MTBF / FIT 率
SN74LV11A-Q1D Green (RoHS & no Sb/Br)  CU NIPDAU  Level-1-260C-UNLIM SN74LV11A-Q1D SN74LV11A-Q1D
SN74LV11A-Q1DE4 Pb-Free (RoHS)  CU NIPDAU  Level-1-260C-UNLIM SN74LV11A-Q1DE4 SN74LV11A-Q1DE4
SN74LV11A-Q1 应用技术支持与电子电路设计开发资源下载
  1. SN74LV11A-Q1 数据资料 dataSheet 下载.PDF
  2. TI 德州仪器门电路产品选型与价格 . xls
  3. Logic Guide 2009 (PDF 4263 KB)
  4. Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
  5. Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
  6. TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
  7. Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
  8. CMOS Power Consumption and CPD Calculation (PDF 89 KB)
  9. Designing With Logic (PDF 186 KB)
  10. Live Insertion (PDF 150 KB)
  11. Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
  12. Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
  13. HiRel Unitrode Power Management Brochure (PDF 206 KB)
  14. LOGIC Pocket Data Book (PDF 6001 KB)
  15. HiRel Unitrode Power Management Brochure (PDF 206 KB)
  16. Logic Cross-Reference (PDF 2938 KB)