SN74LVC00A 四路 2 输入正与非门
The SN54LVC00A quadruple 2-input positive-NAND gate is designed for 2.7-V to 3.6-V VCC operation, and the SN74LVC00A quadruple 2-input positive-NAND gate is designed for 1.65-V to 3.6-V VCC operation.
The 'LVC00A devices perform the Boolean function Y = A • B or Y = A + B in positive logic.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators in a mixed 3.3-V/5-V system environment.
| SN74LVC00A | |
| Rating | Catalog |
| Technology Family | LVC |
SN74LVC00A 特性
- Operate From 1.65 V to 3.6 V
- Specified From -40°C to 85°C, -40°C to 125°C, and -55°C to 125°C
- Inputs Accept Voltages to 5.5 V
- Max tpd of 4.3 ns at 3.3 V
- Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C
- Typical VOHV (Output VOH Undershoot)
>2 V at VCC = 3.3 V, TA = 25°C - Latch-Up Performance Exceeds 250 mA Per JESD 17
- ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)
SN74LVC00A 芯片订购指南
| 器件 | 状态 | 温度 | 价格 | 封装 | 引脚 | 封装数量 | 封装载体 | 丝印标记 |
| SN74LVC00AD | ACTIVE | -40 to 85 | 0.20 | 1ku | SOIC (D) | 14 | 50 | TUBE | 74LVC00A |
| SN74LVC00ADE4 | ACTIVE | -40 to 85 | 0.20 | 1ku | SOIC (D) | 14 | 50 | TUBE | 74LVC00A |
| SN74LVC00ADG4 | ACTIVE | -40 to 85 | 0.20 | 1ku | SOIC (D) | 14 | 50 | TUBE | 74LVC00A |
| SN74LVC00ADR | ACTIVE | 0 to 70 | 0.26 | 1ku | SOIC (D) | 14 | 2500 | LARGE T&R | 74LVC00A |
| SN74LVC00ADRE4 | ACTIVE | 0 to 70 | 0.26 | 1ku | SOIC (D) | 14 | 2500 | LARGE T&R | 74LVC00A |
| SN74LVC00ADRG4 | ACTIVE | 0 to 70 | 0.26 | 1ku | SOIC (D) | 14 | 2500 | LARGE T&R | 74LVC00A |
| SN74LVC00AN | ACTIVE | 0 to 70 | 0.95 | 1ku | PDIP (N) | 14 | 20 | TUBE | SN74LVC00AN |
| SN74LVC00ANE4 | ACTIVE | 0 to 70 | 0.95 | 1ku | PDIP (N) | 14 | 20 | TUBE | SN74LVC00AN |
SN74LVC00A 质量与无铅数据
| 器件 | 环保计划* | 铅/焊球涂层 | MSL 等级/回流焊峰 | 环保信息与无铅 (Pb-free) | DPPM / MTBF / FIT 率 |
| SN74LVC00AD | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74LVC00AD | SN74LVC00AD |
| SN74LVC00ADE4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74LVC00ADE4 | SN74LVC00ADE4 |
| SN74LVC00ADG4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74LVC00ADG4 | SN74LVC00ADG4 |
| SN74LVC00ADR | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74LVC00ADR | SN74LVC00ADR |
| SN74LVC00ADRE4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74LVC00ADRE4 | SN74LVC00ADRE4 |
| SN74LVC00ADRG4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74LVC00ADRG4 | SN74LVC00ADRG4 |
| SN74LVC00AN | Pb-Free (RoHS) | CU NIPDAU | N/A for Pkg Type | SN74LVC00AN | SN74LVC00AN |
| SN74LVC00ANE4 | Pb-Free (RoHS) | CU NIPDAU | N/A for Pkg Type | SN74LVC00ANE4 | SN74LVC00ANE4 |
SN74LVC00A 应用技术支持与电子电路设计开发资源下载
- SN74LVC00A 数据资料 dataSheet 下载.PDF
- TI 德州仪器门电路产品选型与价格 . xls
- Logic Guide 2009 (PDF 4263 KB)
- Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
- Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
- TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
- Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
- CMOS Power Consumption and CPD Calculation (PDF 89 KB)
- Designing With Logic (PDF 186 KB)
- Live Insertion (PDF 150 KB)
- Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
- Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- LOGIC Pocket Data Book (PDF 6001 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- Logic Cross-Reference (PDF 2938 KB)
