SN74LVC112A 具有清零和预设功能的双路下降沿 J-K 触发器
This dual negative-edge-triggered J-K flip-flop is designed for 1.65-V to 3.6-V VCC operation.
A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the J and K inputs meeting the setup-time requirements is transferred to the outputs on the negative-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the J and K inputs can be changed without affecting the levels at the outputs. The SN74LVC112A can perform as a toggle flip-flop by tying J and K high.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators in a mixed 3.3-V/5-V system environment
| SN74LVC112A | |
| Voltage Nodes(V) | 3.3, 2.7, 2.5, 1.8 |
| Technology Family | LS |
| Rating | Catalog |
SN74LVC112A 特性
- Operates From 1.65 V to 3.6 V
- Inputs Accept Voltages to 5.5 V
- Max tpd of 4.8 ns at 3.3 V
- Typical VOLP (Output Ground Bounce)
<0.8 V at VCC = 3.3 V, TA = 25°C - Typical VOHV (Output VOH Undershoot)
>2 V at VCC = 3.3 V, TA = 25°C - Latch-Up Performance Exceeds 250 mA Per JESD 17
- ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)
SN74LVC112A 芯片订购指南
| 器件 | 状态 | 温度 | 价格 | 封装 | 引脚 | 封装数量 | 封装载体 | 丝印标记 |
| SN74LVC112AD | ACTIVE | 0 to 70 | 0.90 | 1ku | SOIC (D) | 16 | 40 | TUBE | LVC112A |
| SN74LVC112ADE4 | ACTIVE | 0 to 70 | 0.90 | 1ku | SOIC (D) | 16 | 40 | TUBE | LVC112A |
| SN74LVC112ADG4 | ACTIVE | 0 to 70 | 0.90 | 1ku | SOIC (D) | 16 | 40 | TUBE | LVC112A |
| SN74LVC112AN | ACTIVE | 0 to 70 | 0.85 | 1ku | PDIP (N) | 16 | 25 | TUBE | SN74LVC112AN |
| SN74LVC112ANE4 | ACTIVE | 0 to 70 | 0.85 | 1ku | PDIP (N) | 16 | 25 | TUBE | SN74LVC112AN |
| SN74LVC112ANSR | ACTIVE | 0 to 70 | 0.85 | 1ku | SO (NS) | 16 | 2000 | LARGE T&R | LVC112A |
| SN74LVC112ANSRE4 | ACTIVE | 0 to 70 | 0.85 | 1ku | SO (NS) | 16 | 2000 | LARGE T&R | LVC112A |
| SN74LVC112ANSRG4 | ACTIVE | 0 to 70 | 0.85 | 1ku | SO (NS) | 16 | 2000 | LARGE T&R | LVC112A |
SN74LVC112A 质量与无铅数据
| 器件 | 环保计划* | 铅/焊球涂层 | MSL 等级/回流焊峰 | 环保信息与无铅 (Pb-free) | DPPM / MTBF / FIT 率 |
| SN74LVC112AD | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74LVC112AD | SN74LVC112AD |
| SN74LVC112ADE4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74LVC112ADE4 | SN74LVC112ADE4 |
| SN74LVC112AN | Pb-Free (RoHS) | CU NIPDAU | N/A for Pkg Type | SN74LVC112AN | SN74LVC112AN |
| SN74LVC112ANE4 | Pb-Free (RoHS) | CU NIPDAU | N/A for Pkg Type | SN74LVC112ANE4 | SN74LVC112ANE4 |
| SN74LVC112ANSR | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74LVC112ANSR | SN74LVC112ANSR |
| SN74LVC112ANSRE4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74LVC112ANSRE4 | SN74LVC112ANSRE4 |
| SN74LVC112ANSRG4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74LVC112ANSRG4 | SN74LVC112ANSRG4 |
SN74LVC112A 应用技术支持与电子电路设计开发资源下载
- SN74LVC112A 数据资料 dataSheet 下载.PDF
- TI 德州仪器触发器/锁存器/寄存器产品选型与价格 . xls
- Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
- Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
- TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
- Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
- CMOS Power Consumption and CPD Calculation (PDF 89 KB)
- Designing With Logic (PDF 186 KB)
- Live Insertion (PDF 150 KB)
- Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
- Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- LOGIC Pocket Data Book (PDF 6001 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- Logic Cross-Reference (PDF 2938 KB)
