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SN74LVC1G125-EP 具有三态输出的增强型产品单路总线缓冲器闸

This bus buffer gate is designed for 1.65-V to 5.5-V VCC operation.

The SN74LVC1G125 is a single line driver with a 3-state output. The output is disabled when the output-enable (OE) input is high.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver

	SN74LVC1G125-EP
Pin/Package	5SC70
Operating Temperature Range(°C)	-40 to 85,-55 to 125
IOL(mA)	32
Voltage Nodes(V)	1.8, 2.5, 3.3, 5
IOH(mA)	-32
Input Level
Vcc max(V)	5.5
Technology Family	LVC
Vcc min(V)	1.65
tpd max(ns)	4
ICC(uA)	10

SN74LVC1G125-EP 特性

• Controlled Baseline
  • One Assembly/Test Site, One Fabrication Site
• Enhanced Diminishing Manufacturing Sources (DMS) Support
• Enhanced Product-Change Notification
• Qualification Pedigree(1)Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits.
• Supports 5-V VCC Operation
• Inputs Accept Voltages to 5.5 V
• Max tpd of 3.7 ns at 3.3 V
• Low Power Consumption, 10-µA Max ICC
• ±24-mA Output Drive at 3.3 V
• Ioff Supports Partial-Power-Down Mode Operation
• Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
• ESD Protection Exceeds JESD 22
  • 2000-V Human-Body Model (A114-A)
  • 200-V Machine Model (A115-A)
  • 1000-V Charged-Device Model (C101)

SN74LVC1G125-EP 芯片订购指南

器件	状态	温度	价格	封装 | 引脚	封装数量 | 封装载体	丝印标记
CLVC1G125IDCKREP	ACTIVE	-40 to 85	0.29 | 1ku	SC70 (DCK) | 5	3000 | LARGE T&R
CLVC1G125MDCKREP	ACTIVE	-55 to 125	0.37 | 1ku	SC70 (DCK) | 5	3000 | LARGE T&R
CLVC1G125MDCKREPG4	ACTIVE	-55 to 125	0.37 | 1ku	SC70 (DCK) | 5	3000 | LARGE T&R
V62/04735-01XE	ACTIVE	-40 to 85	0.29 | 1ku	SC70 (DCK) | 5	3000 | LARGE T&R
V62/04735-02XE	ACTIVE	-55 to 125	0.37 | 1ku	SC70 (DCK) | 5	3000 | LARGE T&R

SN74LVC1G125-EP 质量与无铅数据

器件	环保计划*	铅/焊球涂层	MSL 等级/回流焊峰	环保信息与无铅 (Pb-free)	DPPM / MTBF / FIT 率
CLVC1G125IDCKREP	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-1-260C-UNLIM	CLVC1G125IDCKREP	CLVC1G125IDCKREP
CLVC1G125MDCKREP	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-1-260C-UNLIM	CLVC1G125MDCKREP	CLVC1G125MDCKREP
CLVC1G125MDCKREPG4	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-1-260C-UNLIM	CLVC1G125MDCKREPG4	CLVC1G125MDCKREPG4
V62/04735-01XE	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-1-260C-UNLIM	V62/04735-01XE	V62/04735-01XE
V62/04735-02XE	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-1-260C-UNLIM	V62/04735-02XE	V62/04735-02XE

SN74LVC1G125-EP 应用技术支持与电子电路设计开发资源下载

1. SN74LVC1G125-EP 数据资料 dataSheet 下载.PDF
2. TI 德州仪器小尺寸逻辑器件产品选型与价格 . xls
3. Logic Guide 2009 (PDF 4263 KB)
4. Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
5. Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
6. TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
7. Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
8. CMOS Power Consumption and CPD Calculation (PDF 89 KB)
9. Designing With Logic (PDF 186 KB)
10. Live Insertion (PDF 150 KB)
11. Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
12. Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
13. HiRel Unitrode Power Management Brochure (PDF 206 KB)
14. LOGIC Pocket Data Book (PDF 6001 KB)
15. HiRel Unitrode Power Management Brochure (PDF 206 KB)
16. Logic Cross-Reference (PDF 2938 KB)