SN74LVC1G97-EP 增强型产品可配置多功能门
This configurable multiple-function gate is designed for 1.65-V to 5.5-V VCC operation.
The SN74LVC1G97 features configurable multiple functions. The output state is determined by eight patterns of 3-bit input. The user can choose the logic functions MUX, AND, OR, NAND, NOR, inverter, and noninverter. All inputs can be connected to VCC or GND.
This device functions as an independent gate, but because of Schmitt action, it may have different input threshold levels for positive-going (VT+) and negative-going (VT–) signals.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down
| SN74LVC1G97-EP | |
| tpd max(ns) | 5.1 |
| Pin/Package | 6SC70 |
| IOH(mA) | -32 |
| IOL(mA) | 32 |
| Voltage Nodes(V) | 1.8, 2.5, 3.3, 5 |
| Vcc min(V) | 1.65 |
| Vcc max(V) | 5.5 |
| Operating Temperature Range(°C) | -40 to 85 |
| Technology Family | LVC |
| No. of Gates | 1 |
| ICC(uA) | 10 |
| Rating | HiRel Enhanced Product |
SN74LVC1G97-EP 特性
- Controlled Baseline
- One Assembly/Test Site, One Fabrication Site
- Enhanced Diminishing Manufacturing Sources (DMS) Support
- Enhanced Product-Change Notification
- Qualification Pedigree
- Supports 5-V VCC Operation
- Inputs Accept Voltages to 5.5 V
- Max tpd of 6.3 ns at 3.3 V
- Low Power Consumption, 10-µA Max ICC
- ±24-mA Output Drive at 3.3 V
- Ioff Supports Partial-Power-Down Mode Operation
- Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
- ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)
- Choose From Nine Specific Logic Functions
SN74LVC1G97-EP 芯片订购指南
| 器件 | 状态 | 温度 | 价格 | 封装 | 引脚 | 封装数量 | 封装载体 | 丝印标记 |
| SN74LVC1G97IDCKREP | ACTIVE | -40 to 85 | 0.19 | 1ku | SC70 (DCK) | 6 | 3000 | LARGE T&R | |
| V62/03642-01XE | ACTIVE | -40 to 85 | 0.19 | 1ku | SC70 (DCK) | 6 | 3000 | LARGE T&R |
SN74LVC1G97-EP 质量与无铅数据
| 器件 | 环保计划* | 铅/焊球涂层 | MSL 等级/回流焊峰 | 环保信息与无铅 (Pb-free) | DPPM / MTBF / FIT 率 |
| SN74LVC1G97IDCKREP | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74LVC1G97IDCKREP | SN74LVC1G97IDCKREP |
| V62/03642-01XE | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | V62/03642-01XE | V62/03642-01XE |
SN74LVC1G97-EP 应用技术支持与电子电路设计开发资源下载
- SN74LVC1G97-EP 数据资料 dataSheet 下载.PDF
- TI 德州仪器小尺寸逻辑器件产品选型与价格 . xls
- Logic Guide 2009 (PDF 4263 KB)
- Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
- Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
- TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
- Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
- CMOS Power Consumption and CPD Calculation (PDF 89 KB)
- Designing With Logic (PDF 186 KB)
- Live Insertion (PDF 150 KB)
- Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
- Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- LOGIC Pocket Data Book (PDF 6001 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- Logic Cross-Reference (PDF 2938 KB)
