The SN74LVC2G125 is a dual bus buffer gate, designed for 1.65-V to 5.5-V VCC operation. This device features dual line drivers with 3-state outputs. The outputs are disabled when the associated output-enable (OE) input is high.
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To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down
SN74LVC2G125 | |
Pin/Package | 8DSBGA |
Operating Temperature Range(°C) | -40 to 85 |
IOL(mA) | 32 |
IOH(mA) | -32 |
Input Level | CMOS |
Vcc max(V) | 5.5 |
Technology Family | LVC |
Vcc min(V) | 1.65 |
Approx. Price (US$) | 0.18 | 1ku |
Output Level | CMOS |
No. of Gates | 2 |
tpd max(ns) | 3.7 |
ICC(uA) | 10 |
Rating | Catalog |
器件 | 状态 | 温度 | 价格(美元) | 封装 | 引脚 | 封装数量 | 封装载体 | 丝印标记 |
SN74LVC2G125YZPR | ACTIVE | -40 to 85 | 0.22 | 1ku | DSBGA (YZD) | 8 | 3000 | LARGE T&R |
器件 | 环保计划* | 铅/焊球涂层 | MSL 等级/回流焊峰 | 环保信息与无铅 (Pb-free) | DPPM / MTBF / FIT 率 |
SN74LVC2G125YZPR | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74LVC2G125YZPR | SN74LVC2G125YZPR |