SN74LVTH240-EP 具有三态输出的增强型产品 3.3V Abt 16 位缓冲器/驱动器

This octal buffer and line driver is designed specifically for low-voltage (3.3-V) VCC operation, but with the capability to provide a TTL interface to a 5-V system environment.

This device is organized as two 4-bit buffer/line drivers with separate output-enable (OE)\ inputs. When OE is low, the device passes data from the A inputs to the Y outputs. When OE\ is high, the outputs are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended

	SN74LVTH240-EP
Voltage Nodes (V)	3.3, 2.7
Vcc range (V)	2.7 to 3.6
Input Level	TTL/CMOS
Output Level	LVTTL
No. of Outputs	8
Output Drive (mA)	-32/64
tpd max (ns)	4
Static Current	5
Logic	Inverting
Technology Family	LVT
Rating	HiRel Enhanced Product
Pin/Package	20TSSOP

SN74LVTH240-EP 特性

Controlled Baseline
- One Assembly/Test Site, One Fabrication Site
Enhanced Diminishing Manufacturing Sources (DMS) Support
Enhanced Product-Change Notification
Qualification Pedigree
Supports Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V VCC)
Supports Unregulated Battery Operation Down to 2.7 V
Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C
Ioff and Power-Up 3-State Support Hot Insertion
Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
Latch-Up Performance Exceeds 500 mA Per JESD 17
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)

SN74LVTH240-EP 芯片订购指南

器件	状态	温度	价格（美元）	封装 \| 引脚	封装数量 \| 封装载体	丝印标记
SN74LVTH240IPWREP	ACTIVE	-40 to 85	0.55 \| 1ku	TSSOP (PW) \| 20	2000 \| LARGE T&R
V62/04672-01XE	ACTIVE	-40 to 85	0.55 \| 1ku	TSSOP (PW) \| 20	2000 \| LARGE T&R

SN74LVTH240-EP 应用手册

标题	类型	大小
选择合适的德州仪器 (TI) 信号开关	PDF	1091
Shelf-Life Evaluation of Lead-Free Component Finishes	PDF	1310
Understanding and Interpreting Standard-Logic Data Sheets	PDF	857
TI IBIS File Creation, Validation, and Distribution Processes	PDF	380
Implications of Slow or Floating CMOS Inputs	PDF	101
CMOS Power Consumption and CPD Calculation	PDF	89
Designing With Logic	PDF	186
Live Insertion	PDF	150
Input and Output Characteristics of Digital Integrated Circuits	PDF	1708
SN54/74HCT CMOS Logic Family Applications and Restrictions	PDF	102
Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc	PDF	43

SN74LVTH240-EP 质量与无铅数据

器件	环保计划*	铅/焊球涂层	MSL 等级/回流焊峰	环保信息与无铅 (Pb-free)	DPPM / MTBF / FIT 率
SN74LVTH240IPWREP	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-1-260C-UNLIM	SN74LVTH240IPWREP	SN74LVTH240IPWREP
V62/04672-01XE	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-1-260C-UNLIM	V62/04672-01XE	V62/04672-01XE