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SN74S112A 具有清零和预设功能的双路 J-K 下降沿触发器

These devices contain two independent J-K negative-edge-triggered flip-flops. A low level at the preset and clear inputs sets or resets the outputs regardless of the levels of the other inputs. When preset and clear are inactive (high), data at the J and K inputs meeting the setup time requirements are transferred to the outputs on the negative-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold time interval, data at the J and K inputs may be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops by tying J and K high.

The SN54LS112A and SN54S112 are characterized for operation over the full military temperature range of -55°C to 125°C

	SN74S112A
Voltage Nodes(V)	5
Technology Family	LS
Rating	Catalog

SN74S112A 特性

• Fully Buffered to Offer Maximum Isolation from External Disturbance
• Package Options Include Plastic “Small Outline" Packages, Ceramic Chip Carriers and Flat Packages, and Plastic and Ceramic DIPs
• Dependable Texas Instruments Quality and Reliability

SN74S112A 芯片订购指南

器件	状态	温度	价格	封装 | 引脚	封装数量 | 封装载体	丝印标记
SN74S112AD	ACTIVE	0 to 70	0.90 | 1ku	SOIC (D) | 16	40 | TUBE	S112A
SN74S112ADE4	ACTIVE	0 to 70	0.90 | 1ku	SOIC (D) | 16	40 | TUBE	S112A
SN74S112ADG4	ACTIVE	0 to 70	0.90 | 1ku	SOIC (D) | 16	40 | TUBE	S112A
SN74S112AN	ACTIVE	0 to 70	0.85 | 1ku	PDIP (N) | 16	25 | TUBE	SN74S112AN
SN74S112ANE4	ACTIVE	0 to 70	0.85 | 1ku	PDIP (N) | 16	25 | TUBE	SN74S112AN
SN74S112ANSR	ACTIVE	0 to 70	0.85 | 1ku	SO (NS) | 16	2000 | LARGE T&R	S112A
SN74S112ANSRE4	ACTIVE	0 to 70	0.85 | 1ku	SO (NS) | 16	2000 | LARGE T&R	S112A
SN74S112ANSRG4	ACTIVE	0 to 70	0.85 | 1ku	SO (NS) | 16	2000 | LARGE T&R	S112A

SN74S112A 质量与无铅数据

器件	环保计划*	铅/焊球涂层	MSL 等级/回流焊峰	环保信息与无铅 (Pb-free)	DPPM / MTBF / FIT 率
SN74S112AD	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-1-260C-UNLIM	SN74S112AD	SN74S112AD
SN74S112ADE4	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-1-260C-UNLIM	SN74S112ADE4	SN74S112ADE4
SN74S112AN	Pb-Free (RoHS)	CU NIPDAU	N/A for Pkg Type	SN74S112AN	SN74S112AN
SN74S112ANE4	Pb-Free (RoHS)	CU NIPDAU	N/A for Pkg Type	SN74S112ANE4	SN74S112ANE4
SN74S112ANSR	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-1-260C-UNLIM	SN74S112ANSR	SN74S112ANSR
SN74S112ANSRE4	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-1-260C-UNLIM	SN74S112ANSRE4	SN74S112ANSRE4
SN74S112ANSRG4	Green (RoHS & no Sb/Br)	CU NIPDAU	Level-1-260C-UNLIM	SN74S112ANSRG4	SN74S112ANSRG4

SN74S112A 应用技术支持与电子电路设计开发资源下载

1. SN74S112A 数据资料 dataSheet 下载.PDF
2. TI 德州仪器触发器/锁存器/寄存器产品选型与价格 . xls
3. Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
4. Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
5. TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
6. Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
7. CMOS Power Consumption and CPD Calculation (PDF 89 KB)
8. Designing With Logic (PDF 186 KB)
9. Live Insertion (PDF 150 KB)
10. Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
11. Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
12. HiRel Unitrode Power Management Brochure (PDF 206 KB)
13. LOGIC Pocket Data Book (PDF 6001 KB)
14. HiRel Unitrode Power Management Brochure (PDF 206 KB)
15. Logic Cross-Reference (PDF 2938 KB)