CD40194B CMOS 4 位双向通用移位寄存器
CD40194B is a universal shift register featuring parallel inputs, parallel outputs SHIFT RIGHT and SHIFT LEFT serial inputs, and a direct overriding clear input. In the parallel-load mode (S0 and S1 are high), data is loaded into the associated flip-flop and appears at the output after the positive transition of the CLOCK input. During loading, serial data flow is inhibited. Shift right and shift left are accomplished synchronously on the positive clock edge with data entered at the SHIFT RIGHT and SHIFT LEFT serial inputs, respectively. Clocking of the register is inhibited when both mode control inputs are low. When low, the RESET\ input resets all stages and forces all outputs low.
The CD40194B types are supplied in 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (NSR suffix), and 16-lead thin shrink small-outline packages (PW and PWR suffixes).
|
CD40194B |
| Voltage Nodes(V) |
5, 10, 15 |
| Technology Family |
CD4000 |
| Rating |
Catalog |
CD40194B 特性
- Medium-speed: fCL = 12 MHz (typ.) @ VDD = 10 V
- Fully static operation
- Synchronous parallel or serial operation
- Asynchronous master reset
- Standardized, symmetrical output characteristics
- 5-V, 10-V, and 15-V parametric ratings
- Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of 'B' Series CMOS Devices"
- Applications
- Arithmetic unit bus registers
- Serial/parallel conversions
- General-purpose register for bus-organized systems
- General-purpose registers
CD40194B 芯片订购指南
| 器件 |
状态 |
温度 |
价格 |
封装 | 引脚 |
封装数量 | 封装载体 |
丝印标记 |
| CD40194BE |
ACTIVE |
-55 to 125 |
0.35 | 1ku |
PDIP (N) | 16 |
25 | TUBE |
CD40194BE |
| CD40194BEE4 |
ACTIVE |
-55 to 125 |
0.35 | 1ku |
PDIP (N) | 16 |
25 | TUBE |
CD40194BE |
CD40194B 质量与无铅数据
| 器件 |
环保计划* |
铅/焊球涂层 |
MSL 等级/回流焊峰 |
环保信息与无铅 (Pb-free) |
DPPM / MTBF / FIT 率 |
| CD40194BE |
Pb-Free (RoHS) |
CU NIPDAU |
N/A for Pkg Type |
CD40194BE |
CD40194BE |
| CD40194BEE4 |
Pb-Free (RoHS) |
CU NIPDAU |
N/A for Pkg Type |
CD40194BEE4 |
CD40194BEE4 |
CD40194B 应用技术支持与电子电路设计开发资源下载
- CD40194B 数据资料 dataSheet 下载.PDF
- TI 德州仪器触发器/锁存器/寄存器产品选型与价格 . xls
- Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
- Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
- TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
- Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
- CMOS Power Consumption and CPD Calculation (PDF 89 KB)
- Designing With Logic (PDF 186 KB)
- Live Insertion (PDF 150 KB)
- Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
- Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- LOGIC Pocket Data Book (PDF 6001 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- Logic Cross-Reference (PDF 2938 KB)
