CD4031B-MIL CMOS 64 级静态移位寄存器
CD4031B is a static shift register that contains 64 D-type, master-slave flip-flop stages and one stage which is a D-type master flip-flop only (referred to as a 1/2 stage).
The logic level present at the DATA input is transferred into the first stage and shifted one stage at each positive-going clock transition. Maximum clock frequencies up to 12 Megahertz (typical) can be obtained. Because fully static operation is allowed, information can be permanently stored with the clock line in either the low or high state. The CD4031B has a MODE CONTROL input that, when in the high state, allows operation in the recirculating mode. The MODE CONTROL input can also be used to select between two separate data sources. Register packages can be cascaded and the clock lines driven directly for high-speed operation
|
CD4031B-MIL |
| Voltage Nodes(V) |
5, 10, 15 |
| Technology Family |
CD4000 |
| Rating |
Catalog |
CD4031B-MIL 特性
- Fully static operation: DC to 12 MHz typ. @ VDD - VSS = 15 V
- Standard TTL drive capability on Q output
- Recirculation capability
- Three cascading modes:
- Direct clocking for high-speed operation
- Delayed clocking for reduced clock drive requirements
- Additional 1/2 stage for slow clocks
- 100% tested for quiescent current at 20 V
- Maximum input current of 1 µA at 18 V over full package-temperature range; 100nA at 18 V and 25°C
- Noise margin (over full package-temperature range):
1 V at VDD = 5 V
2 V at VDD = 10 V
2.5 V at VDD = 15 V
- 5-V, 10-V, and 15-V parametric ratings
- Meets all requirements of JEDEC Tentative Standard No. 13A, "Standard Specifications for Description of 'B' Series CMOS Devices"
- Applications:
- Serial shift register
- Time delay circuits
CD4031B-MIL 芯片订购指南
| 器件 |
状态 |
温度 |
价格 |
封装 | 引脚 |
封装数量 | 封装载体 |
丝印标记 |
| CD4031BF |
ACTIVE |
-55 to 125 |
4.33 | 1ku |
CDIP (JT) | 16 |
1 | TUBE |
|
| CD4031BF3A |
ACTIVE |
-55 to 125 |
5.10 | 1ku |
CDIP (JT) | 16 |
1 | TUBE |
|
CD4031B-MIL 质量与无铅数据
| 器件 |
环保计划* |
铅/焊球涂层 |
MSL 等级/回流焊峰 |
环保信息与无铅 (Pb-free) |
DPPM / MTBF / FIT 率 |
| CD4031BF |
TBD |
A42 |
N/A for Pkg Type |
CD4031BF |
CD4031BF |
| CD4031BF3A |
TBD |
A42 |
N/A for Pkg Type |
CD4031BF3A |
CD4031BF3A |
CD4031B-MIL 应用技术支持与电子电路设计开发资源下载
- CD4031B-MIL 数据资料 dataSheet 下载.PDF
- TI 德州仪器触发器/锁存器/寄存器产品选型与价格 . xls
- Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
- Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
- TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
- Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
- CMOS Power Consumption and CPD Calculation (PDF 89 KB)
- Designing With Logic (PDF 186 KB)
- Live Insertion (PDF 150 KB)
- Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
- Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- LOGIC Pocket Data Book (PDF 6001 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- Logic Cross-Reference (PDF 2938 KB)
