CD4042B CMOS 四路时钟“D”锁存器
CD4042B types contain four latch circuits, each strobed by a common clock. Complementary buffered outputs are available from each circuit. The impedance of the n- and p-channel output devices is balanced and all outputs are electrically identical.
Information present at the data input is transferred to outputs Q and Q\ during the CLOCK level which is programmed by the POLARITY input. For POLARITY = 0 the transfer occurs during the 0 CLOCK level and for POLARITY = 1 the transfer occurs during the 1 CLOCK level. The outputs follow the data input providing the CLOCK and POLARITY levels defined above are present. When a CLOCK transition occurs (positive for POLARITY = 0 and negative for POLARITY = 1) the information present at the input during the CLOCK transition is retained at the output until an opposite CLOCK transition occurs
|
CD4042B |
| Voltage Nodes(V) |
5, 10, 15 |
| Rating |
Military |
| Technology Family |
CD4000 |
CD4042B 特性
- Clock polarity control
- Q and Q\ outputs
- Common Clock
- Low power TTL compatible
- Standardized, symmetrical output characteristics
- 100% tested for quiescent current at 20 V
- Maximum input current of 1 µA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C
- 5-V, 10-V, and 15-V parametric ratings
- Noise margin (full package-temperature range) =
1 V at VDD = 5 V
2 V at VDD = 10 V
2.5 V at VDD = 15 V
- Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of ’B’ Series CMOS Devices"
- Applications:
- Buffer storage
- Holding register
- General digital logic
CD4042B 芯片订购指南
| 器件 |
状态 |
温度 |
价格 |
封装 | 引脚 |
封装数量 | 封装载体 |
丝印标记 |
| CD4042BD |
ACTIVE |
-55 to 125 |
0.36 | 1ku |
SOIC (D) | 16 |
40 | TUBE |
CD4042BM |
| CD4042BDE4 |
ACTIVE |
-55 to 125 |
0.36 | 1ku |
SOIC (D) | 16 |
40 | TUBE |
CD4042BM |
| CD4042BDG4 |
ACTIVE |
-55 to 125 |
0.36 | 1ku |
SOIC (D) | 16 |
40 | TUBE |
CD4042BM |
| CD4042BDR |
ACTIVE |
-55 to 125 |
0.31 | 1ku |
SOIC (D) | 16 |
2500 | LARGE T&R |
CD4042BM |
| CD4042BDRE4 |
ACTIVE |
-55 to 125 |
0.31 | 1ku |
SOIC (D) | 16 |
2500 | LARGE T&R |
CD4042BM |
| CD4042BDRG4 |
ACTIVE |
-55 to 125 |
0.31 | 1ku |
SOIC (D) | 16 |
2500 | LARGE T&R |
CD4042BM |
| CD4042BDT |
ACTIVE |
-55 to 125 |
0.80 | 1ku |
SOIC (D) | 16 |
250 | SMALL T&R |
CD4042BM |
| CD4042BDTE4 |
ACTIVE |
-55 to 125 |
0.80 | 1ku |
SOIC (D) | 16 |
250 | SMALL T&R |
CD4042BM |
| CD4042BDTG4 |
ACTIVE |
-55 to 125 |
0.80 | 1ku |
SOIC (D) | 16 |
250 | SMALL T&R |
CD4042BM |
| CD4042BDW |
ACTIVE |
-55 to 125 |
0.36 | 1ku |
SOIC (DW) | 16 |
40 | TUBE |
CD4042BM |
| CD4042BDWE4 |
ACTIVE |
-55 to 125 |
0.36 | 1ku |
SOIC (DW) | 16 |
40 | TUBE |
CD4042BM |
| CD4042BDWG4 |
ACTIVE |
-55 to 125 |
0.36 | 1ku |
SOIC (DW) | 16 |
40 | TUBE |
CD4042BM |
| CD4042BE |
ACTIVE |
-55 to 125 |
0.35 | 1ku |
PDIP (N) | 16 |
25 | TUBE |
CD4042BE |
| CD4042BEE4 |
ACTIVE |
-55 to 125 |
0.35 | 1ku |
PDIP (N) | 16 |
25 | TUBE |
CD4042BE |
| CD4042BF3AS2329 |
OBSOLETE |
|
|
CDIP (J) | 16 |
|
|
| CD4042BF3AS2534 |
OBSOLETE |
|
|
CDIP (J) | 16 |
|
|
| CD4042BM |
OBSOLETE |
-55 to 125 |
|
SOIC (D) | 16 |
|
|
| CD4042BNSR |
ACTIVE |
-55 to 125 |
0.34 | 1ku |
SO (NS) | 16 |
2000 | LARGE T&R |
CD4042B |
| CD4042BNSRE4 |
ACTIVE |
-55 to 125 |
0.34 | 1ku |
SO (NS) | 16 |
2000 | LARGE T&R |
CD4042B |
| CD4042BNSRG4 |
ACTIVE |
-55 to 125 |
0.34 | 1ku |
SO (NS) | 16 |
2000 | LARGE T&R |
CD4042B |
| CD4042BPW |
ACTIVE |
-55 to 125 |
0.36 | 1ku |
TSSOP (PW) | 16 |
90 | TUBE |
CM042B |
| CD4042BPWE4 |
ACTIVE |
-55 to 125 |
0.36 | 1ku |
TSSOP (PW) | 16 |
90 | TUBE |
CM042B |
| CD4042BPWG4 |
ACTIVE |
-55 to 125 |
0.36 | 1ku |
TSSOP (PW) | 16 |
90 | TUBE |
CM042B |
CD4042B 质量与无铅数据
| 器件 |
环保计划* |
铅/焊球涂层 |
MSL 等级/回流焊峰 |
环保信息与无铅 (Pb-free) |
DPPM / MTBF / FIT 率 |
| CD4042BD |
Green (RoHS & no Sb/Br) |
CU NIPDAU |
Level-1-260C-UNLIM |
CD4042BD |
CD4042BD |
| CD4042BDE4 |
Green (RoHS & no Sb/Br) |
CU NIPDAU |
Level-1-260C-UNLIM |
CD4042BDE4 |
CD4042BDE4 |
| CD4042BDG4 |
Green (RoHS & no Sb/Br) |
CU NIPDAU |
Level-1-260C-UNLIM |
CD4042BDG4 |
CD4042BDG4 |
| CD4042BDR |
Green (RoHS & no Sb/Br) |
CU NIPDAU |
Level-1-260C-UNLIM |
CD4042BDR |
CD4042BDR |
| CD4042BDRE4 |
Green (RoHS & no Sb/Br) |
CU NIPDAU |
Level-1-260C-UNLIM |
CD4042BDRE4 |
CD4042BDRE4 |
| CD4042BDRG4 |
Green (RoHS & no Sb/Br) |
CU NIPDAU |
Level-1-260C-UNLIM |
CD4042BDRG4 |
CD4042BDRG4 |
| CD4042BDT |
Green (RoHS & no Sb/Br) |
CU NIPDAU |
Level-1-260C-UNLIM |
CD4042BDT |
CD4042BDT |
| CD4042BDTE4 |
Green (RoHS & no Sb/Br) |
CU NIPDAU |
Level-1-260C-UNLIM |
CD4042BDTE4 |
CD4042BDTE4 |
| CD4042BDTG4 |
Green (RoHS & no Sb/Br) |
CU NIPDAU |
Level-1-260C-UNLIM |
CD4042BDTG4 |
CD4042BDTG4 |
| CD4042BDW |
Green (RoHS & no Sb/Br) |
CU NIPDAU |
Level-1-260C-UNLIM |
CD4042BDW |
CD4042BDW |
| CD4042BDWE4 |
Green (RoHS & no Sb/Br) |
CU NIPDAU |
Level-1-260C-UNLIM |
CD4042BDWE4 |
CD4042BDWE4 |
| CD4042BDWG4 |
Green (RoHS & no Sb/Br) |
CU NIPDAU |
Level-1-260C-UNLIM |
CD4042BDWG4 |
CD4042BDWG4 |
| CD4042BE |
Pb-Free (RoHS) |
CU NIPDAU |
N/A for Pkg Type |
CD4042BE |
CD4042BE |
| CD4042BEE4 |
Pb-Free (RoHS) |
CU NIPDAU |
N/A for Pkg Type |
CD4042BEE4 |
CD4042BEE4 |
| CD4042BNSR |
Green (RoHS & no Sb/Br) |
CU NIPDAU |
Level-1-260C-UNLIM |
CD4042BNSR |
CD4042BNSR |
| CD4042BNSRE4 |
Green (RoHS & no Sb/Br) |
CU NIPDAU |
Level-1-260C-UNLIM |
CD4042BNSRE4 |
CD4042BNSRE4 |
| CD4042BNSRG4 |
Green (RoHS & no Sb/Br) |
CU NIPDAU |
Level-1-260C-UNLIM |
CD4042BNSRG4 |
CD4042BNSRG4 |
| CD4042BPW |
Green (RoHS & no Sb/Br) |
CU NIPDAU |
Level-1-260C-UNLIM |
CD4042BPW |
CD4042BPW |
| CD4042BPWE4 |
Green (RoHS & no Sb/Br) |
CU NIPDAU |
Level-1-260C-UNLIM |
CD4042BPWE4 |
CD4042BPWE4 |
| CD4042BPWG4 |
Green (RoHS & no Sb/Br) |
CU NIPDAU |
Level-1-260C-UNLIM |
CD4042BPWG4 |
CD4042BPWG4 |
CD4042B 应用技术支持与电子电路设计开发资源下载
- CD4042B 数据资料 dataSheet 下载.PDF
- TI 德州仪器触发器/锁存器/寄存器产品选型与价格 . xls
- Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
- Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
- TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
- Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
- CMOS Power Consumption and CPD Calculation (PDF 89 KB)
- Designing With Logic (PDF 186 KB)
- Live Insertion (PDF 150 KB)
- Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
- Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- LOGIC Pocket Data Book (PDF 6001 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- Logic Cross-Reference (PDF 2938 KB)
