CD4085B-MIL CMOS 双路 2 宽度 2 输入与-或-反向门

CD4085 contains a pair of AND-OR-INVERT gates, each consisting of two 2-input AND gates driving a 3-input NOR gate. Individual inhibit controls are provided for both A-O-I gates.

The CD4085B types are supplied in 14-lead hermetic dual-in-line ceramic packages (F3A suffix), 14-lead dual-in-line plastic packages (E suffix), 14-lead small-outline packages (M, MT, M96, and NSR suffixes), and 14-lead thin shrink small-outline packages (PW and PWR suffixes).

CD4085B-MIL
Voltage Nodes(V) 5, 10, 15  
Rating Catalog  
Technology Family CD4000
CD4085B-MIL 特性
CD4085B-MIL 芯片订购指南
器件 状态 温度 价格 封装 | 引脚 封装数量 | 封装载体 丝印标记
CD4085BF ACTIVE -55 to 125 4.11 | 1ku CDIP (JT) | 14 1 | TUBE  
CD4085BF3A ACTIVE -55 to 125 4.83 | 1ku CDIP (JT) | 14 1 | TUBE  
CD4085B-MIL 质量与无铅数据
器件 环保计划* 铅/焊球涂层 MSL 等级/回流焊峰 环保信息与无铅 (Pb-free) DPPM / MTBF / FIT 率
CD4085BF TBD  A42   N/A for Pkg Type CD4085BF CD4085BF
CD4085BF3A TBD  A42   N/A for Pkg Type CD4085BF3A CD4085BF3A
CD4085B-MIL 应用技术支持与电子电路设计开发资源下载
  1. CD4085B-MIL 数据资料 dataSheet 下载.PDF
  2. TI 德州仪器门电路产品选型与价格 . xls
  3. Logic Guide 2009 (PDF 4263 KB)
  4. Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
  5. Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
  6. TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
  7. Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
  8. CMOS Power Consumption and CPD Calculation (PDF 89 KB)
  9. Designing With Logic (PDF 186 KB)
  10. Live Insertion (PDF 150 KB)
  11. Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
  12. Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
  13. HiRel Unitrode Power Management Brochure (PDF 206 KB)
  14. LOGIC Pocket Data Book (PDF 6001 KB)
  15. HiRel Unitrode Power Management Brochure (PDF 206 KB)
  16. Logic Cross-Reference (PDF 2938 KB)