CD4515B CMOS 4 位锁存器/4 至16 线路解码器
CD4514B and CD4515B consist of a 4-bit strobed latch and a 4-to-16-line decoder. The latches hold the last input data presented prior to the strobe transition from 1 to 0. Inhibit control allows all outputs to be placed at 0 (CD4514B) or 1 (CD4515B) regardless of the state of the data or strobe inputs.
The decode truth table indicates all combinations of data inputs and appropriate selected outputs.
These devices are similar to industry types MC14514 and MC14515.
The CD4514B and CD4515B types are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix), 16-lead dual-in-line plastic packages (E suffix), and 16-lead small-outline packages (M and M96 suffixes).
| CD4515B | |
| Voltage Nodes(V) | 5, 10, 15 |
| Rating | Catalog |
| Technology Family | CD4000 |
CD4515B 特性
CD4514B Output "High" on Select
CD4515B Output "Low" on Select
- Strobed input latch
- Inhibit control
- 100% tested for quiescent current at 20 V
- Maximum input current of 1 µA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C
- Noise margin (over full package temperature range):
- 1 V at VDD = 5 V
- 2 V at VDD = 10 V
- 2.5 V at VDD = 15 V
- 5-V, 10-V, and 15-V parametric ratings
- Standardized, symmetrical output characteristics
- Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of ’B’ Series CMOS Devices"
- Applications:
- Digital multiplexing
- Address decoding
- Hexadecimal/BCD decoding
- Program-counter decoding
- Control decoder
CD4515B 芯片订购指南
| 器件 | 状态 | 温度 | 价格 | 封装 | 引脚 | 封装数量 | 封装载体 | 丝印标记 |
| CD4515BE | ACTIVE | -55 to 125 | 0.33 | 1ku | PDIP (N) | 24 | 25 | TUBE | |
| CD4515BEE4 | ACTIVE | -55 to 125 | 0.33 | 1ku | PDIP (N) | 24 | 25 | TUBE | |
| CD4515BM | ACTIVE | -55 to 125 | 0.34 | 1ku | SOIC(DW) | 24 | 40 | TUBE | |
| CD4515BM96 | ACTIVE | -55 to 125 | 0.28 | 1ku | SOIC(DW) | 24 | 2500 | LARGE T&R | |
| CD4515BM96E4 | ACTIVE | -55 to 125 | 0.28 | 1ku | SOIC(DW) | 24 | 2500 | LARGE T&R | |
| CD4515BM96G4 | ACTIVE | -55 to 125 | 0.28 | 1ku | SOIC(DW) | 24 | 2500 | LARGE T&R | |
| CD4515BME4 | ACTIVE | -55 to 125 | 0.34 | 1ku | SOIC(DW) | 24 | 40 | TUBE | |
| CD4515BMG4 | ACTIVE | -55 to 125 | 0.34 | 1ku | SOIC(DW) | 24 | 40 | TUBE |
CD4515B 质量与无铅数据
| 器件 | 环保计划* | 铅/焊球涂层 | MSL 等级/回流焊峰 | 环保信息与无铅 (Pb-free) | DPPM / MTBF / FIT 率 |
| CD4515BE | Pb-Free (RoHS) | CU NIPDAU | N/A for Pkg Type | CD4515BE | CD4515BE |
| CD4515BEE4 | Pb-Free (RoHS) | CU NIPDAU | N/A for Pkg Type | CD4515BEE4 | CD4515BEE4 |
| CD4515BM | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | CD4515BM | CD4515BM |
| CD4515BM96 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | CD4515BM96 | CD4515BM96 |
| CD4515BM96E4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | CD4515BM96E4 | CD4515BM96E4 |
| CD4515BM96G4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | CD4515BM96G4 | CD4515BM96G4 |
| CD4515BME4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | CD4515BME4 | CD4515BME4 |
| CD4515BMG4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | CD4515BMG4 | CD4515BMG4 |
CD4515B 应用技术支持与电子电路设计开发资源下载
- CD4515B 数据资料 dataSheet 下载.PDF
- TI 德州仪器MSI 功能产品选型与价格 . xls
- Logic Guide 2009 (PDF 4263 KB)
- Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
- Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
- TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
- Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
- CMOS Power Consumption and CPD Calculation (PDF 89 KB)
- Designing With Logic (PDF 186 KB)
- Live Insertion (PDF 150 KB)
- Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
- Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- LOGIC Pocket Data Book (PDF 6001 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- Logic Cross-Reference (PDF 2938 KB)
