CD4517B-MIL CMOS 双路 64 级静态移位寄存器
CD4517B dual 64-stage static shift register consists of two independent registers each having a clock, data, and write enable input and outputs accessible at taps following the 16th, 32nd, 48th, and 64th stages. These taps also serve as input points allowing data to be inputted at the 17th, 33rd, and 49th stages when the write enable input is a logic 1 and the clock goes through a low-to-high transition. The truth table indicates how the clock and write enable inputs control the operation of the CD4517B. Inputs at the intermediate taps allow entry of 64 bits into the register with 16 clock pulses. The 3-state outputs permit connection of this device to an external bus.
The CD4517B is supplied in 16-lead hermetic dual-in-line ceramic packages (D and F suffixes), 16-lead dual-in-line plastic packages (E suffix), and in chip form (H suffix).
|
CD4517B-MIL |
| Voltage Nodes(V) |
5, 10, 15 |
| Technology Family |
CD4000 |
| Rating |
Catalog |
CD4517B-MIL 特性
- Low quiescent current - 10 nA/pkg (typ.) at VDD = 5 V
- Clock frequency 12 MHz (typ.) at VDD = 10 V
- Schmitt trigger clock inputs allow operation with very slow clock rise and fall times
- Capable of driving two low-power TTL loads, one low-power Schottky TTL load, or two HTL loads
- Three-state outputs
- 100% tested for quiescent current at 20 V
- Standardized, symmetrical output characteristics
- 5-V, 10-V and 15-V parametric ratings
- Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of 'B' Series CMOS Devices"
- Applications:
Time-delay circuits
Scratch-pad memories
General-purpose serial shift-register applications
CD4517B-MIL 芯片订购指南
| 器件 |
状态 |
温度 |
价格 |
封装 | 引脚 |
封装数量 | 封装载体 |
丝印标记 |
| CD4517BF |
ACTIVE |
-55 to 125 |
5.09 | 1ku |
CDIP (JT) | 16 |
1 | TUBE |
|
| CD4517BF3A |
ACTIVE |
-55 to 125 |
5.91 | 1ku |
CDIP (JT) | 16 |
1 | TUBE |
|
CD4517B-MIL 质量与无铅数据
| 器件 |
环保计划* |
铅/焊球涂层 |
MSL 等级/回流焊峰 |
环保信息与无铅 (Pb-free) |
DPPM / MTBF / FIT 率 |
| CD4517BF |
TBD |
A42 |
N/A for Pkg Type |
CD4517BF |
CD4517BF |
| CD4517BF3A |
TBD |
A42 |
N/A for Pkg Type |
CD4517BF3A |
CD4517BF3A |
CD4517B-MIL 应用技术支持与电子电路设计开发资源下载
- CD4517B-MIL 数据资料 dataSheet 下载.PDF
- TI 德州仪器触发器/锁存器/寄存器产品选型与价格 . xls
- Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
- Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
- TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
- Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
- CMOS Power Consumption and CPD Calculation (PDF 89 KB)
- Designing With Logic (PDF 186 KB)
- Live Insertion (PDF 150 KB)
- Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
- Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- LOGIC Pocket Data Book (PDF 6001 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- Logic Cross-Reference (PDF 2938 KB)
