TLC3548IDWR 14 位、5V、200KSPS、8 通道单级性 ADC封装SOIC-24
|
TLC3548 |
| Resolution(Bits) |
14 |
| Sample Rate (max) |
200kSPS |
| Architecture |
SAR |
| Power Consumption(Typ)(mW) |
20 |
| SINAD(dB) |
81 |
| SNR(dB) |
81 |
| SFDR(dB) |
97 |
| DNL(Max)(+/-LSB) |
1 |
| INL(Max)(+/-LSB) |
1 |
| No Missing Codes(Bits) |
14 |
| No. of Supplies |
2 |
| Analog Voltage AV/DD(Min)(V) |
4.5 |
| Analog Voltage AV/DD(Max)(V) |
5.5 |
| Logic Voltage DV/DD(Min)(V) |
2.7 |
| Logic Voltage DV/DD(Max)(V) |
5.5 |
| Input Configuration Range |
+4V |
| Reference Mode |
Int and Ext |
| Rating |
Catalog |
| Pin/Package |
24SOIC, 24TSSOP |
| # Input Channels |
8 |
| Operating Temp Range(Celsius) |
-40 to 85,0 to 70 |
The TLC3544 and TLC3548 are a family of 14-bit resolution high-performance, low-power, CMOS analog-to-digital converters (ADC). All devices operate from a single 5-V analog power supply and 3-V to 5-V digital supply. The serial interface consists of four digital inputs [chip select (CS\), frame sync (FS), serial input-output clock (SCLK), serial data input (SDI)], and a 3-state serial data output (SDO). CS\ (works as SS\, slave select), SDI, SDO, and SCLK form an SPI interface. FS, SDI, SDO, and SCLK form a DSP interface. The frame sync signal (FS) indicates the start of a serial data frame being transferred. When multiple converters connect to one serial port of a DSP, CS\ works as the chip select to allow the host DSP to access the individual converter.
TLC3548IDWR 特性
- 14-Bit Resolution
- Maximum Throughput 200 KSPS
- Analog Input Range 0-V to Reference Voltage
- Multiple Analog Inputs:
- 8 Channels for TLC3548
- 4 Channels for TLC3544
- Pseudodifferential Analog Inputs
- SPI/DSP-Compatible Serial Interfaces With SCLK up to 25 MHz
- Single 5-V Analog Supply; 3-/5-V Digital Supply
- Low Power:
- 4 mA (Internal Reference: 1.8 mA) for Normal Operation
- 20 µA in Autopower-Down
- Built-In 4-V Reference, Conversion Clock and 8x FIFO
- Hardware-Controlled and Programmable Sampling Period
- Programmable Autochannel Sweep and Repeat
- Hardware Default Configuration
- INL: ±1 LSB Max
- DNL: ±1 LSB Max
- SINAD: 80.8 dB
- THD: –95 dB
TLC3548IDWR 芯片订购指南
TLC3548IDWR 应用技术支持与电子电路设计开发资源下载
- TLC3548IDWR 数据资料 dataSheet 下载.PDF
- TI 德州仪器仪ADC 模数转换器产品选型与价格 . xls
