TLV320AIC20K 立体声语音频带 (26Ksps) 低功耗编解码器
|
TLV320AIC20K |
TLV320AIC24K |
| SNR DAC / SNR ADC(Typ)(dB) |
92 / 84 |
92 / 84 |
| # DACs / # ADCs |
2 / 2 |
2 / 2 |
| # Inputs / # Outputs |
5 / 4 |
5 / 3 |
| Sampling Rate(Max)(kHz) |
26 |
26 |
| Resolution(Bits) |
16 |
16 |
| Digital Audio Interface |
DSP,SMART TDM |
DSP,SMART TDM |
| Control Interface |
I2C,S2C |
I2C,S2C |
| Analog Supply(V) |
2.7 - 3.6 |
2.7 - 3.6 |
| Digital Supply(V) |
1.65 - 1.95 |
1.65 - 1.95 |
| IO Supply (Volts) |
1.1 - 3.6 |
1.1 - 3.6 |
| Pd(Typ)(mW) |
20 |
20 |
| Additional Features |
8 Ohm Speaker Amplifier |
|
| Operating Temperature Range(°C) |
-40 to 85 |
-40 to 85 |
| Pin/Package |
48TQFP |
48TQFP |
TLV320AIC20K 描述
The TLV320AIC2x is a low-cost, low-power, highly-integrated, high-performance, dual-voice codec. It features two 16-bit analog-to-digital (A/D) channels and two 16-bit digital-to-analog (D/A) channels, which can be connected to a handset, headset, speaker, microphone, or a subscriber line via a programmable analog crosspoint.
The TLV320AIC2x provides high resolution signal conversion from digital-to-analog (D/A) and from analog-to-digital (A/D) using oversampling sigma-delta technology with programmable sampling rate.
The TLV320AIC2x implements the smart time division multiplexed serial port (SMARTDM™). The SMARTDM port is a synchronous 4-wire serial port in TDM format for glue-free interface to TI DSPs (i.
TLV320AIC20K 特性
- Stereo 16-Bit Oversampling Sigma-Delta A/D Converter
- Stereo 16-Bit Oversampling Sigma-Delta D/A Converter
- Support Maximum Master Clock of 100 MHz to Allow DSPs Output Clock to be Used as a Master Clock
- Selectable FIR/IIR Filter With Bypassing Option
- Programmable Sampling Rate up to:
- Max 26 Ksps With On-Chip IIR/FIR Filter
- Max 104 Ksps With IIR/FIR Bypassed
- On-Chip FIR Produced 84-dB SNR for ADC and 92-dB SNR for DAC over 13-Khz BW
- Smart Time Division Multiplexed (SMARTDM®) Serial Port
- Glueless 4-Wire Interface to DSP
- Automatic Cascade Detection (ACD) Self-Generates Master/Slave Device
Addresses
- Programming Mode to Allow On-The-Fly Reconfiguration
- Continuous Data Transfer Mode to Minimize Bit Clock Speed
- Support Different Sampling Rate for Each Device
- Turbo Mode to Maximize Bit Clock For Faster Data Transfer and Allow Multiple Serial Devices to Share the Same Bus
- Allows up to Eight Devices to be Connected to a Single Serial Port
- Host port
- 2-Wire Interface
- Selectable I2C or S2C
- Differential and Single-Ended Analog Input/Output
TLV320AIC20K 芯片订购指南
| 器件 |
状态 |
温度 (oC) |
价格（美元） |
封装 | 引脚 |
封装数量 | 封装载体 |
丝印标记 |
| TLV320A20KIPFBRG4 |
ACTIVE |
-40 to 85 |
2.70 | 1ku |
TQFP (PFB) | 48 |
1000 | LARGE T&R |
320AIC20K |
| TLV320AIC20KIPFB |
ACTIVE |
-40 to 85 |
2.95 | 1ku |
TQFP (PFB) | 48 |
250 | JEDEC TRAY (5+1) |
320AIC20K |
| TLV320AIC20KIPFBG4 |
ACTIVE |
-40 to 85 |
2.95 | 1ku |
TQFP (PFB) | 48 |
250 | JEDEC TRAY (5+1) |
320AIC20K |
| TLV320AIC20KIPFBR |
ACTIVE |
-40 to 85 |
2.70 | 1ku |
TQFP (PFB) | 48 |
1000 | LARGE T&R |
320AIC20K |
TLV320AIC20K 质量与无铅数据
TLV320AIC20K 应用技术支持与电子电路设计开发资源下载
- TLV320AIC20K 数据资料 dataSheet 下载.PDF
- TI 德州仪器音频编解码器产品选型与价格参考 . xls
- 模数规格和性能特性术语表 (Rev. A) (PDF 1993 KB)
- 所选封装材料的热学和电学性质 (PDF 645 KB)
- 高速数据转换 (PDF 1967 KB)
- Shelf-Life Evaluation of Lead-Free Component Finishes (PDF
1305 KB)
- Analog-to-Digital Converter Grounding Practices Affect System
Performance (PDF 56 KB)
- Principles of Data Acquisition and Conversion (PDF 50 KB)
- Interleaving Analog-to-Digital Converters (PDF 64 KB)
- What
Designers Should Know About Data Converter Drift (PDF 95 KB)
- Giving Delta-Sigma Converters a Gain Boost with a Front End
Analog Gain Stage (PDF 70 KB)
- Programming Tricks for Higher Conversion Speeds Utilizing Delta
Sigma Converters (PDF 105 KB)
TLV320AIC20K 工具与软件
