TMS320VC5410A 数字信号处理器
The TMS320VC5410A fixed-point, digital signal processor (DSP) (hereafter referred to as the 5410A unless otherwise specified) is based on an advanced modified Harvard architecture that has one program memory bus and three data memory buses. This processor provides an arithmetic logic unit (ALU) with a high degree of parallelism, application-specific hardware logic, on-chip memory, and additional on-chip peripherals. The basis of the operational flexibility and speed of this DSP is a highly specialized instruction set.
Separate program and data spaces allow simultaneous access to program instructions and data, providing a high degree of parallelism. Two read operations and one write operation can be performed in a single cycle
|
TMS320VC5410A |
| Applications |
Communications and Telecom,Industrial |
| Operating Systems |
DSP/BIOS |
| DSP |
1 C54x |
| DSP Instruction Type |
Fixed Point |
| DSP MHz (Max.) |
120,160 |
| DSP Peak MMACS |
120,160 |
| General Purpose Memory |
Async SRAM |
| HPI |
1 16-bit HPI |
| McBSP |
3 |
| DMA (Ch) |
16-Ch EDMA |
| IO Supply (V) |
3.3 |
| Operating Temperature Range (C) |
-40 to 100 |
| Pin/Package |
144BGA MICROSTAR, 144LQFP |
| Approx. Price (US$) |
14.80 | 1ku |
TMS320VC5410A 特性
- Advanced Multibus Architecture With Three Separate 16-Bit Data Memory Buses and One Program Memory Bus
- 40-Bit Arithmetic Logic Unit (ALU) Including a 40-Bit Barrel Shifter and Two Independent 40-Bit Accumulators
- 17- × 17-Bit Parallel Multiplier Coupled to a 40-Bit Dedicated Adder for Non-Pipelined Single-Cycle Multiply/Accumulate (MAC) Operation
- Compare, Select, and Store Unit (CSSU) for the Add/Compare Selection of the Viterbi Operator
- Exponent Encoder to Compute an Exponent Value of a 40-Bit Accumulator Value in a Single Cycle
- Two Address Generators With Eight Auxiliary Registers and Two Auxiliary Register Arithmetic Units (ARAUs)
- Data Bus With a Bus Holder Feature
- Extended Addressing Mode for 8M × 16-Bit Maximum Addressable External Program Space
- 64K x 16-Bit On-Chip RAM Composed of:
- Eight Blocks of 8K × 16-Bit On-Chip Dual-Access Program/Data RAM
- 16K × 16-Bit On-Chip ROM Configured for Program Memory
- Enhanced External Parallel Interface (XIO2)
- Single-Instruction-Repeat and Block-Repeat Operations for Program Code
- Block-Memory-Move Instructions for Better Program and Data Management
- Instructions With a 32-Bit Long Word Operand
- Instructions With Two- or Three-Operand Reads
- Arithmetic Instructions With Parallel Store and Parallel Load
- Conditional Store Instructions
- Fast Return From Interrupt
- On-Chip Peripherals
TMS320VC5410A 芯片订购指南
TMS320VC5410A 质量与无铅数据
| 器件 |
环保计划* |
铅/焊球涂层 |
MSL 等级/回流焊峰 |
环保信息与无铅 (Pb-free) |
DPPM / MTBF / FIT 率 |
| TMS320VC5410AGGU12 |
TBD |
SNPB |
Level-3-220C-168 HR |
TMS320VC5410AGGU12 |
TMS320VC5410AGGU12 |
| TMS320VC5410AGGU16 |
TBD |
SNPB |
Level-3-220C-168 HR |
TMS320VC5410AGGU16 |
TMS320VC5410AGGU16 |
| TMS320VC5410APGE12 |
Green (RoHS & no Sb/Br) |
CU NIPDAU |
Level-1-260C-UNLIM |
TMS320VC5410APGE12 |
TMS320VC5410APGE12 |
| TMS320VC5410APGE16 |
Green (RoHS & no Sb/Br) |
CU NIPDAU |
Level-1-260C-UNLIM |
TMS320VC5410APGE16 |
TMS320VC5410APGE16 |
| TMS320VC5410AZGU12 |
Green (RoHS & no Sb/Br) |
SNAGCU |
Level-3-260C-168 HR |
TMS320VC5410AZGU12 |
TMS320VC5410AZGU12 |
| TMS320VC5410AZGU16 |
Green (RoHS & no Sb/Br) |
SNAGCU |
Level-3-260C-168 HR |
TMS320VC5410AZGU16 |
TMS320VC5410AZGU16 |
| TMS32DSP5410APGE16 |
Green (RoHS & no Sb/Br) |
CU NIPDAU |
Level-1-260C-UNLIM |
TMS32DSP5410APGE16 |
TMS32DSP5410APGE16 |
TMS320VC5410A 应用技术支持与电子电路设计开发资源下载
- TMS320VC5410A 数据资料 dataSheet 下载.PDF
- TI 德州仪器数字信号处理器 (DSP) & ARM 微处理器选型与价格 . xls
- OMAP-L13x/AM1x Linux PSP Overview
- ARM Assembly Language Tools v4.7 User's Guide
- ARM Optimizing C/C++ Compiler v4.7 User's Guide
- Power Management for AM18xx/AM17xx Processors
- ARM Portfolio Technical Overview Brochure
- Software and Hardware Design Challenges due to Dynamic Raw NAND Market
- Programmable Real-Time Unit (PRU): Extending Functionality Of Existing SoCs
TMS320VC5410A 工具与软件
