TMS320VC5503 定点数字信号处理器
The TMS320VC5503 fixed-point digital signal processor (DSP) is based on the TMS320C55x DSP generation CPU processor core. The C55x™ DSP architecture achieves high performance and low power through increased parallelism and total focus on reduction in power dissipation. The CPU supports an internal bus structure that is composed of one program bus, three data read buses, two data write buses, and additional buses dedicated to peripheral and DMA activity. These buses provide the ability to perform up to three data reads and two data writes in a single cycle. In parallel, the DMA controller can perform up to two data transfers per cycle independent of the CPU activity.
The C55x CPU provides two multiply-accumulate (MAC) units, each capable of 17-bit × 17-bit multiplication in a single cycle.
|
TMS320VC5503 |
| Applications |
Audio,Automotive,Communications and Telecom,Consumer Electronics,Industrial |
| Operating Systems |
DSP/BIOS,VLX |
| DSP |
1 C55x |
| DSP Instruction Type |
Fixed Point |
| DSP MHz (Max.) |
108,144,200 |
| DSP Peak MMACS |
400 |
| General Purpose Memory |
1 16-bit Async SRAM |
| DRAM |
SDRAM |
| USB |
1 |
| I2C |
1 16-bit HPI |
| McBSP |
3 |
| DMA (Ch) |
6-Ch DMA |
| IO Supply (V) |
2.7 to 3.6 |
| Operating Temperature Range (C) |
-40 to 85 |
| Pin/Package |
144LQFP, 179BGA MICROSTAR |
| Approx. Price (US$) |
6.75 | 1ku |
TMS320VC5503 特性
- High-Performance, Low-Power, Fixed-Point TMS320C55™ Digital Signal Processor
- 9.26-, 6.95-, 5-ns Instruction Cycle Time
- 108-, 144-, 200-MHz Clock Rate
- One/Two Instruction(s) Executed per Cycle
- Dual Multipliers [Up to 400 Million Multiply-Accumulates per Second (MMACS)]
- Two Arithmetic/Logic Units (ALUs)
- Three Internal Data/Operand Read Buses and Two Internal Data/Operand Write Buses
- 32K × 16-Bit On-Chip RAM, Composed of:
- 64K Bytes of Dual-Access RAM (DARAM) 8 Blocks of 4K × 16-Bit
- 64K Bytes of One-Wait-State On-Chip ROM (32K × 16-Bit)
- 8M × 16-Bit Maximum Addressable External Memory Space (Synchronous DRAM)
- 16-Bit External Parallel Bus Memory Supporting Either:
- External Memory Interface (EMIF) With GPIO Capabilities and Glueless Interface to:
- Asynchronous Static RAM (SRAM)
- Asynchronous EPROM
- Synchronous DRAM (SDRAM)
- 16-Bit Parallel Enhanced Host-Port Interface (EHPI) With GPIO Capabilities
- Programmable Low-Power Control of Six Device Functional Domains
- On-Chip Scan-Based Emulation Logic
- On-Chip Peripherals
TMS320VC5503 芯片订购指南
TMS320VC5503 质量与无铅数据
| 器件 |
环保计划* |
铅/焊球涂层 |
MSL 等级/回流焊峰 |
环保信息与无铅 (Pb-free) |
DPPM / MTBF / FIT 率 |
| TMS320VC5503GHH |
TBD |
SNPB |
Level-3-220C-168 HR |
TMS320VC5503GHH |
TMS320VC5503GHH |
| TMS320VC5503PGE |
Green (RoHS & no Sb/Br) |
CU NIPDAU |
Level-4-260C-72 HR |
TMS320VC5503PGE |
TMS320VC5503PGE |
| TMS320VC5503ZHH |
Green (RoHS & no Sb/Br) |
SNAGCU |
Level-3-260C-168 HR |
TMS320VC5503ZHH |
TMS320VC5503ZHH |
TMS320VC5503 应用技术支持与电子电路设计开发资源下载
- TMS320VC5503 数据资料 dataSheet 下载.PDF
- TI 德州仪器数字信号处理器 (DSP) & ARM 微处理器选型与价格 . xls
- OMAP-L13x/AM1x Linux PSP Overview
- ARM Assembly Language Tools v4.7 User's Guide
- ARM Optimizing C/C++ Compiler v4.7 User's Guide
- Power Management for AM18xx/AM17xx Processors
- ARM Portfolio Technical Overview Brochure
- Software and Hardware Design Challenges due to Dynamic Raw NAND Market
- Programmable Real-Time Unit (PRU): Extending Functionality Of Existing SoCs
TMS320VC5503 工具与软件
