The ADF4193 frequency synthesizer can be used to implement local oscillators in the up-conversion and down-conversion sections of wireless receivers and transmitters. Its architecture is specifically designed to meet the GSM/EDGE lock time requirements for base stations.
It consists of a low-noise digital phase frequency detector (PFD), and a precision differential charge pump. There is also a differential amplifier (Diff Amp) to convert the differential charge pump output to a single ended voltage for the external voltage controlled oscillator (VCO). The Σ-Δ based fractional interpolator, working with the N divider, allow programmable modulus fractional-N division. Additionally, the 4-bit reference (R) counter and on-chip frequency doubler, allows selectable reference signal (REFIN) frequencies at the PFD input.
A complete phase-locked loop (PLL) can be implemented if the synthesizer is used with an external loop filter and a VCO. The switching architecture ensures that the PLL settles inside the GSM time slot guard period, removing the need for a second PLL and associated isolation switches. This saves cost, complexity, PCB area, shielding and characterization on previous ping-pong GSM PLL architectures.
产品型号 | 产品状态 | 封装 | 引脚 | 温度范围 |
---|---|---|---|---|
ADF4193BCPZ | 量产 | 32 ld LFCSP (5x5mm) w/3.3mm exposed pad | 32 | 商业 |
ADF4193BCPZ-RL | 量产 | 32 ld LFCSP (5x5mm) w/3.3mm exposed pad | 32 | 商业 |
ADF4193BCPZ-RL7 | 量产 | 32 ld LFCSP (5x5mm) w/3.3mm exposed pad | 32 | 商业 |
EVAL-ADF4193EBZ1 | 量产 | 评估板 | - | 待定 |
EVAL-ADF4193EBZ2 | 量产 | 评估板 | - | 待定 |