ATF1502ASV CPLD可编程逻辑器件
| Commercial tpd |
-15 ns,
-20 ns |
| Generic Part . |
1502 |
| I/O Pins |
44 |
| Macrocells |
32 |
| Registers |
32 |
| Usable Gates |
750 |
| Vcc (V) |
3.3 |
| Packages |
PLCC 44
TQFP 44 |
| Pb-Free Packages |
PLCC 44
TQFP 44 |
Low voltage, Vcc- 3.3V, 32 MC, ISP, Green package, CPLD
The ATF1502ASV is a high-performance, high-density complex programmable logic device
(CPLD) that utilizes Atmel’s proven electrically-erasable technology. With 32 logic macrocells
and up to 36 inputs, it easily integrates logic from several TTL, SSI, MSI, LSI and classic PLDs.
The ATF1502ASV’s enhanced routing switch matrices increase usable gate count and the odds
of successful pin-locked design modifications.
The ATF1502ASV has up to 32 bi-directional I/O pins and four dedicated input pins, depending
on the type of device package selected. Each dedicated pin can also serve as a global control
signal, register clock, register reset or output enable. Each of these control signals can be
selected for use individually within each macrocell.
ATF1502ASV 特征
- High-density, High-performance, Electrically-erasable Complex Programmable
Logic Device
– 3.0 to 3.6V Operating Range
– 32 Macrocells
– 5 Product Terms per Macrocell, Expandable up to 40 per Macrocell
– 44 Pins
– 15 ns Maximum Pin-to-pin Delay
– Registered Operation up to 77 MHz
– Enhanced Routing Resources
- In-System Programmability (ISP) via JTAG
- Flexible Logic Macrocell
– D/T Latch Configurable Flip-flops
– Global and Individual Register Control Signals
– Global and Individual Output Enable
– Programmable Output Slew Rate
– Programmable Output Open Collector Option
– Maximum Logic Utilization by Burying a Register with a COM Output
- Advanced Power Management Features
– Pin-controlled 0.75 mA Standby Mode
– Programmable Pin-keeper Inputs and I/Os
– Reduced-power Feature per Macrocell
- Available in Commercial and Industrial Temperature Ranges
- Available in 44-lead PLCC and TQFP
- Advanced EEPROM Technology
– 100% Tested
– Completely Reprogrammable
– 10,000 Program/Erase Cycles
– 20-year Data Retention
– 2000V ESD Protection
– 200 mA Latch-up Immunity
- JTAG Boundary-scan Testing to IEEE Std. 1149.1-1990 and 1149.1a-1993 Supported
- PCI-compliant
- Security Fuse Feature
- Green (Pb/Halide-fee/RoHS Compliant) Package Options
Enhanced Features
- Improved Connectivity (Additional Feedback Routing, Alternate Input Routing)
- Output Enable Product Terms
- D Latch Mode
- Combinatorial Output with Registered Feedback within Any Macrocell
- Three Global Clock Pins
- Fast Registered Input from Product Term
- Programmable “Pin-keeper” Option
- VCC Power-up Reset Option
- Pull-up Option on JTAG Pins TMS and TDI
- Advanced Power Management Features
– Individual Macrocell Power Option
ATF1502ASV 订货型号
ATF1502ASV 应用技术支持与电子电路设计开发资源下载
- ATMEL 爱特梅尔PLD可编程逻辑器件ATF1502ASV 数据手册DataSheet 下载.PDF
- ATMEL 产品选型目录. PDF
- 相关SPLD / CPLD 可编程逻辑选型表
- Atmel CPLD Reference Designs . pdf(White Paper, 17 pages, updated 1/01)
This document describes three full applications using Logic Doubling techniques: 1) 8255 Serial IO expander with IO enable on every pin, 2) Low Power Serial IO expander and 32 LED driver, 3) Four 8-bit PWM generators, bus interface and value latches. Each fits in a 32 macrocell ATF1502 device. It also describes how to add transparent pin latch, ala HC573/373 into a corner of your CPLD. Click here for the Reference Design files for all these designs, plus a fourth Low Power Serial IO expander and 32 LCD driver application that uses each macrocell three ways and a Logic Doubling Tutorial.
- ATF15xx-DK2 CPLD 开发套件用户手册. pdf (User Guide, 47 pages, updated 8/02)
CPLD Development/Programmer Kit User Guide.
- ATF15xx 系列ISP 器件用户手册. pdf (User Guide, 54 pages, updated 7/01)
This document describes in detail the ATDH11xxPC series of ISP Board, Adapter Boards, Atmel's ATMISP software and Atmel's ISP download cable and gives detailed instructions for their use in programming Atmel's ATF15xx family of In-System Programmable CPLDs.
- ATF15xx 系列CPLD概述. pdf
