ATF750LVC-15SU PLD可编程逻辑器件SOIC-24封装
Commercial tpd |
15 |
Generic Part |
750 |
I/O Pins |
24,28 |
Macrocells |
10 |
Power Options |
STANDARD |
Registers |
20 |
Usable Gates |
500 |
Vcc (V) |
3.0, 5.5 |
Pb-Free Packages |
TSSOP 24
PDIP 24
PLCC 28
SOIC (300mil) 24 |
20 FFs, 10 I/O Pins, Vcc of 3.0 - 5.5V, Green package, 750 gates PLD
The Atmel® “750” architecture is twice as powerful as most other 24-pin programmable
logic devices. Increased product terms, sum terms, flip-flops and output logic
configurations translate into more usable gates. High-speed logic and uniform, predictable
delays guarantee fast in-system performance. The ATF750LVC is a highperformance
CMOS (electrically-erasable) complex programmable logic device
(CPLD) that utilizes Atmel’s proven electrically-erasable technology.
ATF750LVC-15SU 特征
- 3.0V to 5.5V Operating Range
- Advanced, High-speed, Electrically-erasable Programmable Logic Device
– Superset of 22V10
– Enhanced Logic Flexibility
– Architecturally Compatible with ATV750B and ATV750 Software and Hardware
- D- or T-type Flip-flop
- Product Term or Direct Input Pin Clocking
- 10 ns Maximum Pin-to-pin Delay with 5V Operation
- 15 ns Maximum Pin-to-pin Delay with 3V Operation
- Highest Density Programmable Logic Available in 24-pin Package
– Advanced Electrically-erasable Technology
– Reprogrammable
– 100% Tested
- Increased Logic Flexibility
– 42 Array Inputs, 20 Sum Terms and 20 Flip-flops
- Enhanced Output Logic Flexibility
– All 20 Flip-flops Feed Back Internally
– 10 Flip-flops are also Available as Outputs
- Programmable Pin-keeper Circuits
- Dual-in-line and Surface Mount Package in Standard Pinouts
- Commercial and Industrial Temperature Ranges
- 20-year Data Retention
- 2000V ESD Protection
- 1000 Erase/Write Cycles
- Green Package Options (Pb/Halide-free/RoHS Compliant) Available
ATF750LVC-15SU 订货型号
ATF750LVC-15SU 应用技术支持与电子电路设计开发资源下载
- ATMEL 爱特梅尔PLD可编程逻辑器件ATF750LVC 数据手册Da0taSheet 下载.PDF
- ATMEL 产品选型目录. PDF
- 相关SPLD / CPLD 可编程逻辑选型表
- Atmel PLDs' Architectures Simplify Timing Calculations . pdf (4 pages, updated 8/99)
This Application Note shows different graphical timing models that can help the user visualize the AC timing of the various Atmel PLD families of devices.
- Saving Power with Atmel PLDs . pdf (7 pages, updated 9/00)
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- Using a PLD as a System Controller in an I/O Bus Based System . pdf (7 pages, updated 9/99)
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- Using the ATV750 and ATV750B . pdf(13 pages, updated 9/99)
This Application Note describes how to use the features of the ATV750 and ATV750B in the ABEL (and Atmel-ABEL) and CUPL (and Atmel-CUPL) high level description languages.
- Migrating from ATV750B/BL to ATF750C/CL . pdf (6 pages, updated 9/08)
This Application Note will assist customers in migrating from the ATV750B/BL PLDs to the ATF750C/CL.