74AHC164：标准逻辑
| Part Number | Data Sheet | SPICE Model | Number of Gates | Family | VCC Min (V) | VCC Max (V) | tpd max @ (1.5V) (ns) | tpd max @ (1.8V) (ns) | tpd max @ (2.5V) (ns) | tpd max @ (3.3V) (ns) | tpd max @ (5.0V) (ns) | Input/ Output Current |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 74AHC164 | 74AHC164.pdf | - | - | AHC | - | - | - | - | - | 16.3 | 11 | - |
Description
The 74AHC164 is a serial input 8-bit edge-triggered shift register that has outputs from each of eight stages.
SERIAL DATA INPUT PINS
The serial input data is entered at pin SDA or pin SDB as these are logically ANDED. Either input could be used as an active HIGH enable with data entry on the other pin. If a single input is desired, the pins can be tied together or the unused input can be tied HIGH.
DATA ENTRY
Data is shifted into Q0 from the serial input pins on each LOW to HIGH transition of the CP pin. Also during the CP edge the data is transferred from each Qn to Qn+1. The serial data on pins DSA and DSB must be stable before and after the CP rising edge to meet the set-up and hold timing requirements.
RESET
When asserted LOW the Master Reset (MR ) pin sets all Qn to LOW. This action does not depend on the condition of serial input or clock pins. The MR must be asserted HIGH for a recovery time before the next CP positive edge pulse.
Application
- General Purpose Logic
- Wide Array of Products Such as:
- PCs, Networking, Notebooks, Netbooks
- Computer Peripherals, Hard Drives, CD/DVD ROM
- TV, DVD, DVR, Set-Top Box
Features
- Wide Supply Voltage Range from 2.0V to 5.5V
- Sinks or Sources 8mA at VCC = 4.5V
- CMOS Low Power Consumption
- Schmitt Trigger Action at All Inputs
- ESD Protection Exceeds JESD 22
- 200-V Machine Model (A115)
- 2000-V Human Body Model (A114)
- Exceeds 1000-V Charged Device Model (C101)
- Range of Package Options SO-14 and TSSOP-14
- Totally Lead-Free & Fully RoHS Compliant
- Halogen and Antimony Free. “Green” Device
订购型号
- 74AHC164D14
- 74AHC164S14-13
TSSOP-14
SO-14
- 74AHC164.pdf 74AHC164
